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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 583-586
Hill , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abuelyamen , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Huang , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Shen , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
ABSTRACT
A novel approach to clock-mode simulation of sequential circuits is introduced. Surrogate fault propagation is used for processing stored faults and extracting new faults from combinational logic. Problem fault types are analyzed and treated as exceptions.
INDEX TERMS
surrogate fault propagation, stored faults processing, two task algorithm, clock mode fault simulation, sequential circuits, combinational logic
CITATION

Hill, Shen, Huang and Abuelyamen, "A new two task algorithm for clock mode fault simulation in sequential circuits," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 583-586.
doi:10.1109/DAC.1988.14820
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