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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 573-578
Xiong , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
ABSTRACT
A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.
INDEX TERMS
Manhattan routeing, grid based routeing, constrained via minimization, PCB, VLSI design, two-layer routing, printed-circuit boards, equivalent graph model, linear-programming formulation, heuristic algorithm, gridless routing, knock-knee routings
CITATION

Kuh and Xiong, "The constrained via minimization problem for PCB and VLSI design," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 573-578.
doi:10.1109/DAC.1988.14818
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