The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 517-522
Boehner , Siemens AG, Munich, West Germany
ABSTRACT
A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.
INDEX TERMS
layout verification, LOGEX, automatic logic extractor, CMOS technology, program, gate-level description, transistor-level description, VLSI circuit, extraction algorithm, gate-level description
CITATION

Boehner, "LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 517-522.
doi:10.1109/DAC.1988.14809
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