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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 506-511
Adler , Silicon Compiler Syst., Liberty Corner, NJ, USA
A model for MOS transistors suitable for logic simulation of VLSI circuits is presented based on the concept of a dynamically directed switch (DDS). In this model, transistors are represented by directed edges in a graph that are capable of changing their direction dynamically. A distributed algorithm for switch-level simulation is presented that is based on an incremental graph algorithm in which edge and vertex labels are updated as a consequence of circuit events. The result is a switch-level algorithm that runs at speeds approaching gate-level logic simulators, while dealing with all the features associated with switch-level simulation: bidirectional signal flow, ratioed logic, RC-tree timing, and correct handling of transistor signal propagation in the presence of unknown signals. The implementation of this algorithm in the Lsim mixed-mode analog and digital simulator is described, and some results and examples are presented.
vertex label updating, mixed mode analogue/digital simulator, dynamically-directed switch model, MOS logic simulation, MOS transistors, VLSI circuits, directed edges, graph, distributed algorithm, switch-level simulation, incremental graph algorithm, bidirectional signal flow, ratioed logic, RC-tree timing, transistor signal propagation, Lsim

Adler, "A dynamically-directed switch model for MOS logic simulation," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 506-511.
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