The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 495-500
Beatty , Carnegie-Mellon Univ., Pittsburgh, PA, USA
Bryant , Carnegie-Mellon Univ., Pittsburgh, PA, USA
ABSTRACT
The authors present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.
INDEX TERMS
processing time reduction, incremental circuit analysis, extracted hierarchy, two-level subnetwork hierarchy, flat netlists, COSMOS, compiled switch-level simulator, file system, hash table, hierarchy extraction algorithm, hash signature, wirelist-comparison programs
CITATION

Beatty and Bryant, "For incremental circuit analysis using extracted hierarchy," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 495-500.
doi:10.1109/DAC.1988.14805
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