The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 489-494
Camposano , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
The automatic synthesis of an IBM 801 processing unit using the Yorktown silicon compiler is presented. The underlying design process model is explained showing the intermediate stages, while emphasizing high-level issues. First, the principles of operations are translated manually into high-level behavioral descriptions. The system is decomposed by the designer into concurrent modules (in the 801, four pipeline stages). Structural synthesis automatically generates a circuit structure for each pipeline stage, including the control and the data path. The combinational logic is optimized globally during logic synthesis producing a multilevel implementation. The resulting size (in number of transistors) and the performance of the processor (estimated cycle time and cycles per instruction) are compared to a manual RT-level design.
CAD, computer aided design, Yorktown silicon compiler, automatic synthesis, IBM 801 processing unit, design process model, high-level behavioral descriptions, concurrent modules, pipeline stages, combinational logic, logic synthesis, multilevel implementation

Camposano, "Design process model in the Yorktown silicon compiler," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 489-494.
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