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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 312-317
Mallela , AT&T Bell Lab., Murray Hill, NJ, USA
Grover , AT&T Bell Lab., Murray Hill, NJ, USA
ABSTRACT
The authors present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. They form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. They then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results of this two-stage simulated annealing have been superior to those with a conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, the authors report a factor-of-two-to-three speed-up in CPU time, together with a 6-to-17% improvement in the estimated wire length.
INDEX TERMS
clustering based simulated annealing, LTX2 VLSI layout system, optimisation technique, standard cell placement, simulated annealing, interconnections, CPU time, wire length
CITATION

Grover and Mallela, "Clustering based simulated annealing for standard cell placement," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 312-317.
doi:10.1109/DAC.1988.14776
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