Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Chang , AT&T Bell Lab., Murray Hill, NJ, USA
Chen , AT&T Bell Lab., Murray Hill, NJ, USA
Subramaniam , AT&T Bell Lab., Murray Hill, NJ, USA
The authors describe an accurate and efficient gate-level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. The highly efficient delay characterization is accomplished through a fast timing simulation technique, a theorem that reduces a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process. The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented.
gate delay models, gate-level delay calculator, gate delays, MOS circuits, waveform slope effects, transmission gate circuits, simulation technique, two-dimensional delay table, scaled one-dimensional table, incremental characterization process, production timing analyzer, production multiple delay simulator, SPICE-like circuit simulator
Chen, Chang and Subramaniam, "An accurate and efficient gate level delay calculator for MOS circuits," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 282-287.