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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 225-230
Saitoh , Fujitsu Ltd., Kawasaki, Japan
Iwata , Fujitsu Ltd., Kawasaki, Japan
Nakamura , Fujitsu Ltd., Kawasaki, Japan
Kakegawa , Fujitsu Ltd., Kawasaki, Japan
Masuda , Fujitsu Ltd., Kawasaki, Japan
Hamamura , Fujitsu Ltd., Kawasaki, Japan
Hirose , Fujitsu Ltd., Kawasaki, Japan
Kawato , Fujitsu Ltd., Kawasaki, Japan
ABSTRACT
A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.
INDEX TERMS
computer design verification, VLSI, special-purpose logic simulation processor, logic devices, hardware architecture, software system, 32 Mbytes
CITATION

Hirose et al., "Logic simulation system using simulation processor (SP)," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 225-230.
doi:10.1109/DAC.1988.14762
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