Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Cai , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
An algorithm is presented for obtaining a planar routing of two power nets in building-block layout. In contrast to other works, more than one pad for each of the power nets is allowed. First, conditions are established to guarantee a planar routing. The algorithm consists of three parts, a top-down terminal clustering, a bottom-up topological path routing, and a wire-width calculation procedure. Because of the hierarchical nature of the algorithm, it is inherently fast.
multipads routing, single layer power net routing, VLSI circuits, algorithm, planar routing, power nets, building-block layout, top-down terminal clustering, bottom-up topological path routing, wire-width calculation procedure
Cai, "Multi-pads, single layer power net routing in VLSI circuits," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 183-188.