Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Lewis , Dept. of Electr. Eng., Toronto Univ., Ont., Canada
A high-performance hardware accelerator is described for electrical simulation, with a speedup of over 500 for a uniprocessor. The processor addresses a variety of problems ranging from timing simulation to circuit simulation. The accelerator combines special purpose units, such as a high-speed device evaluator, with a fully programmable general-purpose processor. The specialized processors offer extremely high speed for performance-critical parts of the simulation. The general-purpose processors are optimized for compiled electrical simulation, and use a very long instruction word (VLIW) architecture. The network solution is compiled into VLIW code. The author concentrates on those features of the machine that are designed for circuit simulation algorithms, such as SPICE. A simplified example is used to expose the hardware and software techniques used to attack the problem, and estimate the performance improvement due to each technique.
very long instruction word architecture, hardware technique, VLSI design, Awsim-3, vector processor, programmable hardware accelerator, compiled electrical simulation, timing simulation, circuit simulation, high-speed device evaluator, programmable general-purpose processor, (VLIW), circuit simulation algorithms, SPICE, software techniques
Lewis, "A programmable hardware accelerator for compiled electrical simulation," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 172-177.