The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 166-171
Soule , Center for Integrated Syst., Stanford Univ., CA, USA
Blank , Center for Integrated Syst., Stanford Univ., CA, USA
Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.
parallel algorithms, logic simulation, general-purpose shared-memory parallel machine, event-driven algorithm, synchronous unit-delay compiled-mode algorithm, asynchronous simulation, simulating circuits

Blank and Soule, "Parallel logic simulation on general purpose machines," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 166-171.
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