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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 160-165
Bailey , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
Snyder , Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
ABSTRACT
A methodology is presented for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.
INDEX TERMS
RISC microprocessors, IIR digital filter, multiplier, shift register, decoder, empirical study, on-chip parallelism, CMOS VLSI chip, circuit size, parallel simulators
CITATION

Bailey and Snyder, "An empirical study of on-chip parallelism," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 160-165.
doi:10.1109/DAC.1988.14752
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