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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 148-153
Cherry , Symbolics Cambridge Res. Center, MA, USA
ABSTRACT
Pearl is a timing analyzer that has been used to verify both full-custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error-free clock period and duty cycles. The author describes the mechanism used to determine the timing relationship each node in the circuit has with respect to the clock edges. He then shows how these dependencies, together with the setup and hold time requirements of latches and registers in the circuit, are used to formulate timing constraints between the clock edges. These timing requirements are solved using a linear programming algorithm to determine the minimum time of each clock edge. The algorithm is first described for the case of a circuit composed of functional models and then applied to MOS switch circuits. The author also describes transistor signal-flow direction rules for CMOS circuits used to eliminate false paths.
INDEX TERMS
logic analysers, VLSI, timing verification, CMOS timing analyzer, Pearl, full-custom VLSI, gate array designs, minimum error-free clock period, duty cycles, hold time requirements, latches, registers, timing constraints, timing requirements, linear programming algorithm, minimum time of each clock edge, MOS switch circuits, transistor signal-flow direction rules, CMOS circuits, eliminate false paths
CITATION

Cherry, "Pearl: a CMOS timing analyzer," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 148-153.
doi:10.1109/DAC.1988.14750
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