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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 142-147
Li , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
ABSTRACT
The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches.
INDEX TERMS
timing verification, design automation, path selection in combinational logic circuits, polynomial-time algorithm, minimum cardinality path set, sequential circuits, scan design
CITATION

Li, Reddy and Sahni, "On path selection in combinational logic circuits," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 142-147.
doi:10.1109/DAC.1988.14749
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