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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 128-133
Zargham , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
ABSTRACT
A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.
INDEX TERMS
parallel channel routing, circuit layout CAD, parallel algorithm, switchbox routing, design of VLSI chips, shared-memory multiprocessor environment
CITATION

Zargham, "Parallel channel routing," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 128-133.
doi:10.1109/DAC.1988.14747
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