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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 121-127
Kumar , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Sastry , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
ABSTRACT
The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal solutions for the smaller problems into a near-optimal solution for the original placement problem. The algorithm lends itself very naturally to a parallel realization, and maps nicely onto an SIMD (single-instruction, multiple data-stream) organization. Considerations such as cost-effectiveness and suitability to VLSI implementation led to the selection of the reduced array architecture as the target architecture for the placement accelerator.
INDEX TERMS
parallel placement, reduced array architecture, hardware accelerator, module placement algorithm, divide-and-conquer paradigm, partitioning algorithm, approximate solution, large placement problem, near-optimal solution, parallel realization, cost-effectiveness, suitability to VLSI implementation, placement accelerator
CITATION

Kumar and Sastry, "Parallel placement on reduced array architecture," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 121-127.
doi:10.1109/DAC.1988.14746
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