Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Sechen , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
The algorithms and the implementation of a novel macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the area around the individual cells is determined using novel interconnect area estimator. The second stage consists of: (1) a channel definition step, using a novel channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect-length savings of 8 to 49% were achieved in experiments on nine industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56% versus a variety of other placement methods.
cell placement, custom cells, macro cells, cell chip-planning, global routing package, simulated-annealing-based placement algorithm, interconnect area estimator, channel definition step, channel definition algorithm, global routing step, placement refinement step, interconnect-length savings, circuit-area reductions
Sechen, "Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 73-80.