Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
Wimer , Dept. of Electr. Eng., Technion, Israel Inst. of Technol., Israel
A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.
layout area minimisation, VLSI, optimal implementation, building block, polynomial algorithm, slicing floorplans, branch-and-bound algorithm, large general nonslicing floorplans, very large general floorplans
Cederbaum, Koren and Wimer, "Optimal aspect ratios of building blocks in VLSI," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 66-71.