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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 54-59
Chen , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Bushnell , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
ABSTRACT
An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.
INDEX TERMS
design iterations reduction, standard cell layout, area estimation, module area estimator, VLSI layout, VLSI chip layout, chip floor plan, full-custom layout, layout area estimates
CITATION

Chen and Bushnell, "A module area estimator for VLSI layout," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 54-59.
doi:10.1109/DAC.1988.14734
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