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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 48-53
Augustin , Comput. Syst. Lab., Stanford Univ., CA, USA
Gennart , Comput. Syst. Lab., Stanford Univ., CA, USA
Huh , Comput. Syst. Lab., Stanford Univ., CA, USA
Luckham , Comput. Syst. Lab., Stanford Univ., CA, USA
Stanculescu , Comput. Syst. Lab., Stanford Univ., CA, USA
ABSTRACT
VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL. An overview is given of design checking using VAL. VAL is described in detail and it is shown how VAL annotations are used to generate constraints on a VHDL simulation. A brief overview of the VAL transformer demonstrates the feasibility of the design. Some observations based on experience with VAL to date and areas for future work are considered.
INDEX TERMS
VHDL Annotation Language, language constructs, VHSIC Hardware Description Language, VAL annotations, formal comments, expressive language extension, automatic checking of VHDL simulations, hierarchical design, automatic verification of hardware designs, design checking using VAL, constraints, VHDL simulation, feasibility
CITATION

Augustin, Gennart, Huh, Stanculescu and Luckham, "Verification of VHDL designs using VAL," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 48-53.
doi:10.1109/DAC.1988.14733
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