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Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 22-27
Wehn , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Glesner , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Caesar , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Mann , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Roth , Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
ABSTRACT
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.
INDEX TERMS
yield, VLSI, defect tolerant PLA, design for testability, fully testable PLA, programmable logic array, repair process, location of defects, defect location mechanism
CITATION

Roth, Wehn, Caesar, Mann and Glesner, "A defect-tolerant and fully testable PLA," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 22-27.
doi:10.1109/DAC.1988.14729
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