The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 16-21
Gebotys , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
Elmasry , Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
ABSTRACT
A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example has been used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST (built-in-self-testing) with different test schedules have been explored. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.
INDEX TERMS
area constraints, logic CAD, circuit layout CAD, design for testability, top-down design, bottom-up design, VLSI design synthesis, delay constraints, binary tree data structure, testable design search, datapath allocation, constraint estimation, feedback for design exploration, partitioning, two-dimensional characteristics, VLSI design floorplans, global information, test incorporation, elliptical wave filter example, testability constraints, multiple chain scan paths, BIST, built-in-self-testing, test schedules
CITATION

Elmasry and Gebotys, "VLSI design synthesis with testability," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 16-21.
doi:10.1109/DAC.1988.14728
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