The Community for Technology Leaders
Design Automation Conference (1988)
Anaheim, CA, USA
June 12, 1988 to June 15, 1988
ISBN: 0-8186-0864-1
pp: 3-8
Stroud , AT&T Bell Lab., Naperville, IL, USA
ABSTRACT
An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.
INDEX TERMS
design for testability, automated BIST approach, general sequential logic synthesis, built-in self-test, behavioral model synthesis system, automated implementation of BIST, very-large-scale-integration, programmable-logic-device, PLD, all levels of testing, device testing, system diagnostics, selective replacement of existing system memory elements, BIST flip-flop cells, circular chain, data compaction, test pattern generation, production VLSI devices, total fault coverage, logic overhead
CITATION

Stroud, "An automated BIST approach for general sequential logic synthesis," Design Automation Conference(DAC), Anaheim, CA, USA, 1988, pp. 3-8.
doi:10.1109/DAC.1988.14726
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