The Community for Technology Leaders
Design Automation Conference (1987)
Miami Beach, Florida, USA USA
June 28, 1987 to July 1, 1987
ISSN: 0738-100X
ISBN: 0-8186-0781-5
TABLE OF CONTENTS

A Fast Signature Simulation Tool for Built-In Self-Testing Circuits (Abstract)

S.B. Tan , GEC Research Limited, Hirst Research Centre, Wembley, Middlesex, United Kingdom
pp. 17-25

An Improved Systematic Method for Constructing Systolic Arrays from Algorithms (Abstract)

N. Faroughi , Department of Electrical Engineering, Michigan State University, East Lansing, MI
pp. 26-34

Predicting Area-Time Tradeoffs for Pipelined Design (Abstract)

R. Jain , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 35-41

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (Abstract)

R. Harjani , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
pp. 42-49

Standard Cell Placement Using Simulated Sintering (Abstract)

L.K. Grover , AT&T Bell Laboratories, Murray Hill, NJ
pp. 56-59

ESP: A New Standard Cell Placement Package Using Simulated Evolution (Abstract)

R.-M. Kling , Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign
pp. 60-66

Requirements for a Practical Software Engineering Environment (Abstract)

V. Masurkar , Wang Laboratories, Inc., Lowell, MA
pp. 67-73

The Making of VIVID A Software Engineering Perspective (Abstract)

J.B. Rosenberg , Duke University Department of Computer Science, Durham, NC
pp. 74-81

A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (Abstract)

N.J. Elias , Philips Laboratories North American, Philips Corporation
pp. 82-88

A Hardware Switch Level Simulator for Large MOS Circuits (Abstract)

M.T. Smith , Hewlett Packard Laboratories, Palo Alto, CA
pp. 95-100

Circuit Simulation on the Connection Machine (Abstract)

D.M. Webber , University of California, Berkeley
pp. 108-113

Aesop: A Tool for Automated Transistor Sizing (Abstract)

K.S. Hedlund , Department of Computer Science, University of North Carolina, Chapel Hill, NC
pp. 114-120

Transistor Sizing in CMOS Circuits (Abstract)

M.A. Cirit , Silicon Design Labs, Liberty Corner, NJ
pp. 121-124

Delay Optimization of Combinational Static CMOS Logic (Abstract)

M. Hofmann , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 125-132

Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic (Abstract)

R.E. Canright , Martin Marietta Orlando Aerospace, Orlando, FL
pp. 133-139

Routing L-Shaped Channels in Nonslicing-Structure Placement (Abstract)

H.H. Chen , Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA
pp. 152-158

Via Minimization for Gridless Layouts (Abstract)

N.J. Naclerio , Electrical Engineering Department and Systems Research Center, University of Maryland, College Park, MD
pp. 159-165

An Overview of Logic Synthesis Systems (PDF)

L. Trevillyan , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 166-172

Realistic Fault Modeling for VLSI Testing (PDF)

W. Maly , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 173-180

Demand Driven Simulation: BACKSIM (Abstract)

S.P. Smith , Microelectronics and Computer Technology Corporation
pp. 181-187

Force-Directed Scheduling in Automatic Data Path Synthesis (Abstract)

P.G. Pauline , Bell-Northern Research, Ottawa, ONT.
pp. 195-202

Knowledge Based Control in Micro-Architecture Design (Abstract)

F.D. Brewer , Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 203-209

REAL: A Program for REgister ALlocation (Abstract)

F.J. Kurdahi , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 210-215

A Practical Moat Router (Abstract)

R.K. McGehee , Seattle Silicon Corporation, Bellevue, WA
pp. 216-222

An Automated Design of Minimum-Area IC Power/Ground Nets (Abstract)

S. Chowdhury , Department of Electrical & Computer Engineering, The University of Iowa, Iowa City, IA
pp. 223-229

Abstract Routing of Logic Networks for Custom Module Generation (Abstract)

S.T. Healey , Kuck and Associates, Savoy, IL 61874 and Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 230-236

On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates (Abstract)

R. Rajsuman , Department of Electrical Engineering, Colorado State University, Fort Collins, CO
pp. 244-250

Integrating Design Information for IC Diagnosis (Abstract)

S.E. Concina , SENTRY Schlumberger, San Jose, CA
pp. 251-257

Switch Directed Dynamic Causal Networks -- A Paradigm for Electronic System Diagnosis (Abstract)

R.M. McDermott , ITT/CGE ALCATEL Advanced Technology Center, Shelton, Connecticut
pp. 258-264

Functional Verification of MOS Circuits (Abstract)

D. Weise , Stanford University Computer Systems Laboratory, Center for Integrated Systems, Stanford, CA
pp. 265-270

On The Verification of Sequential Machines at Differing Levels of Abstraction (Abstract)

S. Devadas , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 271-276

Application of Term Rewriting Techniques to Hardware Design Verification (Abstract)

M.S. Chandrasekhar , Hewlett-Packard Company Design Technology Laboratory, Palo Alto, CA
pp. 277-282

Logic Verification Algorithms and their Parallel Implementation (Abstract)

H.-K.T. Ma , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 283-290

Generating Incremental VLSI Compaction Spacing Constraints (Abstract)

C.W. Carpenter , Stanford University, Stanford CA
pp. 291-297

Improving Virtual-Grid Compaction Through Grouping (Abstract)

L.S. Nyland , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 305-310

KAHLUA: A Hierarchical Circuit Disassembler (Abstract)

B. Lin , Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California Berkeley, CA
pp. 311-317

Benchmarks for Cell-Based Layout Systems (PDF)

B. Preas , Xerox PARC, Palo Alto, CA
pp. 319-320

VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data (Abstract)

R. Bhateja , Computer Science Division, Electrical Engineering and Computer Science Department, University of California, Berkeley, Berkeley, CA
pp. 321-327

DAGON: Technology Binding and Local Optimization by DAG Matching (Abstract)

K. Keutzer , AT&T Bell Laboratories, Murray Hill, NJ
pp. 341-347

Finding the Optimal Variable Ordering for Binary Decision Diagrams (Abstract)

S.J. Friedman , Dept. of Computer Science, Princeton University, Princeton, NJ
pp. 348-356

Mesh Arrays and Logician: A Tool for Their Efficient Generation (Abstract)

J.A. Beekman , Department of Computer Science, The Pennsylvania State University, University Park, PA
pp. 357-362

Strip Layout: A New Layout Methodology for Standard Circuit Modules (Abstract)

J. Apte , Computer Science Department, Duke University, Durham, NC
pp. 363-369

The ALGIC Silicon Compiler System: Implementation, Design Experience and Results (Abstract)

J. Schuck , Technical University of Darmstadt Institut fuer Halbleitertechnik, Darmstadt, FR Germany
pp. 370-375

On Computing Optimized Input Probabilities for Random Tests (Abstract)

H.-J. Wunderlich , Universitat Karlsruhe Institut fur Informatik, Karlsruhe, FRG
pp. 392-398

VLSI Circuit Testing Using an Adaptive Optimization Model (Abstract)

P.S. Yu , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 399-406

Circular Self-Test Path: A Low-Cost BIST Technique (Abstract)

A. Krasniewski , The Technical University of Warsaw Institute of Telecommunications, Warszawa, Poland
pp. 407-415

PHRAN-SPAN: A Natural Language Interface for System Specifications (Abstract)

J. Granacki , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 416-422

TED: A Graphical Technology Description Editor (Abstract)

W. Lee , VHSIC Test Systems SENTRY Schlumberger, San Jose, CA
pp. 423-428

"?": A Context-Sensitive Help System Based on Hypertext (Abstract)

W. Lee , VHSIC Test Systems, SENTRY Schlumberger, San Jose, CA
pp. 429-435

VISION: VHDL Induced Schematic Imaging on Net-Lists (Abstract)

R.K. Chun , TRW Electronic Systems Group and UCLA Computer Science Department
pp. 436-442

Fast, Small, and Static Combinatorial CMOS Circuits (Abstract)

B.P. Serlet , Xerox PARC Computer Science Laboratory, Palo Alto, CA
pp. 451-458

LCS-A Leaf Cell Synthesizer Employing Formal Deduction Techniques (Abstract)

P.A. Subrahmanyam , AT&T Bell Laboratories, Holmdel, NJ
pp. 459-465

A Design Rule Independent Cell Compiler (Abstract)

J.S.J. Chen , Integrated Computer Aided Design Inc., Sunnyvale, CA
pp. 466-471

An Interface between VHDL and EDIF (Abstract)

M. Shahdad , CAD Language Systems, Inc., Rockville, MD
pp. 472-478

The IBM VHDL Design System (Abstract)

L.F. Saunders , IBM System Products Division, North Rochester, MN
pp. 484-490

Where VHDL Fits within the CAD Environment (Abstract)

J. Hines , AFWAL/AAD VHSIC PO, Wright-Patterson AFB OH
pp. 491-494

A Hierarchical Approach to Test Vector Generation (Abstract)

S.J. Chandra , Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL
pp. 495-501

A Topological Search Algorithm for ATPG (Abstract)

T. Kirkland , MCC, Dr. Austin, TX
pp. 502-508

Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits (Abstract)

M. Ladjadj , Center for Integrated Electronics, Rensselaer Polytechnic Institute
pp. 509-515

An Overview of the Penn State Design System (Abstract)

R.M. Owens , Department of Computer Science, Penn State University, University Park, PA
pp. 516-522

ASTA: LSI Design Management System (Abstract)

T. Ogihara , Mitsubishi Electric Corporation, Kanagawa, JAPAN
pp. 530-536

Array Optimization for VLSI Synthesis (Abstract)

D.F. Wong , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 537-543

The Design Automation Standards Environment (PDF)

R. Waxman , Center for Semicustom Integrated Systems, School of Engineering and Applied Science, University of Virginia, Charlottesville, VA
pp. 559-561

Design Automation Standards Need Integration (PDF)

L. O'Connell , Sandia National Laboratories, Albuquerque, NM
pp. 562

REDS: Resistance Extraction for Digital Simulation (Abstract)

D. Stark , Center for Integrated Systems, Stanford University, Stanford, CA
pp. 570-573

Function Search from Behavioral Description of a Digital System (Abstract)

J.-G. Wu , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX
pp. 574-579

The Implementation of a State Machine Compiler (Abstract)

C. Kingsley , VLSI Technology, Centre de Recherche Europeen, Sophia-Antipolis, Valbonne, France
pp. 580-583

Boolean Comparison by Simulation (Abstract)

E.P. Stabler , Syracuse University
pp. 584-587

Statistics for Parallelism and Abstraction Level in Digital Simulation (Abstract)

L. Soule , Stanford University Center for Integrated Systems
pp. 588-591

A Conceptual Framework for Designing ASIC Hardware (Abstract)

S.S. Leung , Department of Electrical Engineering, Michigan State University, East Lansing, MI
pp. 592-595

CASE: An Integrated Design Environment for Algorithm-Driven Architectures (Abstract)

D.C.A. Bulterman , LABORATORY FOR ENGINEERING MAN-MACHINE SYSTEMS, Division of Engineering, Brown University
pp. 596-599

A Parallel PLA Minimization Program (Abstract)

R. Galivanche , Motorola Inc. Chandler, AZ
pp. 600-607

Improving a PLA Area by Pull-Up Transistor Folding (Abstract)

C. Lursinsap , The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA
pp. 608-614

Routing with a Scanning Window - A Unified Approach (Abstract)

D. Kaplan , Intel Corporation, Santa Clara, CA
pp. 629-632

General Purpose Router (Abstract)

R.J. Enbody , Dept. of Computer Science, University of Minnesota, Minneapolis, MN
pp. 637-640

A New Compaction Scheme Based on Compression Ridges (Abstract)

Pradip.C. Shah , DEPT OF CS & E, INDIAN INSTITUTE OF TECHNOLOGY, MADRAS, INDIA
pp. 645-648

Hierarchical Design Based on a Calculus of Nets (Abstract)

B. Becker , Universitat des Saarlandes, Saarbrucken, FRG
pp. 649-653

An Application of Exploratory Data Analysis Techniques to Floorplan Design (Abstract)

E.F.M. Kouka , Circuits and Systems Laboratory, GRENOBLE, FRANCE
pp. 654-658

PAMS: An Expert System for Parameterized Module Synthesis (Abstract)

T. Cesear , Hughes Aircraft Company, Hughes Microelectronics Center, Carlsbad, CA
pp. 666-671

LES: A Layout Expert System (Abstract)

Y.-L.S. Lin , Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 672-678

An Expert System Application in Semicustom VLSI Design (Abstract)

R.L. Steele , NCR Microelectronics, Fort Collins, CO
pp. 679-686

Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories (Abstract)

P. Mazumder , Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana, IL
pp. 688-694

A Dynamic Programming Approach to the Test Point Insertion Problem (Abstract)

B. Krishnamurthy , Computer Research Laboratory, Tektronix Laboratories, Beaverton, OR
pp. 695-705

A Parts Selection Expert System to Increase Manufacturability (Abstract)

D. Praizler , Hewlett-Packard Company, Ft. Collins, CO
pp. 706-712

Fast Printed Circuit Board Routing (Abstract)

J. Dion , Digital Equipment Corporation, Western Research Laboratory, Palo Alto, CA
pp. 727-734

Heuristic Acceleration of Force-Directed Placement (Abstract)

R. Forbes , Hewlett-Packard Company
pp. 735-740

EASE: A Design Support Environment for the HDDL ELLA (Abstract)

J.D. Morison , UK Ministry of Defence Royal Signals and Radar Establishment, Malvern, Worcestershire
pp. 741-749

CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools (Abstract)

L.-P. Demers , Dept. d'informatique et de recherche operationnelle, Universite de Montreal, Montreal, Que., Canada
pp. 750-756

STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct (Abstract)

E.F. Girczyc , Department of Electrical Engineering, University of Alberta, Edmonton, Alberta, Canada
pp. 757-763

A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts (Abstract)

A.A. Minai , Center for Semicustom Integrated Systems, University of Virginia, Charlottesville, VA
pp. 770-776

A Rule-Based Placement System for Printed Wiring Boards (Abstract)

G. Odawara , Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Tokyo, JAPAN
pp. 777-785

A Rule-Based Circuit Representation for Automated CMOS Design and Verification (Abstract)

C.-F.E. Wu , Department of Computer Science, Michigan State University, East Lansing, MI
pp. 786-792

A High Performance Routing Engine (Abstract)

T.D. Spiers , University of Manchester, U.K.
pp. 793-799

Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube (Abstract)

M. Jones , Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
pp. 807-813

A Preliminary Investigation into Parallel Routing on a Hypercube Computer (Abstract)

O.A. Olukotun , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
pp. 814-820

Functional Abstraction from Structure in VLSI Simulation Models (Abstract)

R.H. Lathrop , MIT Artificial Intelligence Laboratory, Cambridge, MA
pp. 822-828

Optimal Layout to Avoid CMOS Stuck-Open Faults (Abstract)

S. Koeppe , Siemens AG, Research Laboratories, Munich, FRG
pp. 829-834

Reviewers (PDF)

pp. 836,837
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