The Community for Technology Leaders
Design Automation Conference (1986)
Las Vegas, Nevada, USA USA
June 29, 1986 to July 2, 1986
ISSN: 0738-100X
ISBN: 0-8186-0702-5
TABLE OF CONTENTS

Fundamentals of Parallel Logic Simulation (PDF)

R.J. Smith , Microelectronics and Computer Technology Corporation, Austin, TX
pp. 2-12

Statistics on Logic Simulation (PDF)

K.F. Wong , Center For Computer Systems Design, Washington University, St. Louis, Missouri
pp. 13-19

Exploiting Parallelism in a Switch-Level Simulation Machine (Abstract)

E.H. Frank , Austek Microsystems, Technology Park, Adelaide, SA, Australia
pp. 20-26

A Version Server for Computer-Aided Design Data (PDF)

R.H. Katz , Computer Science Division, Electrical Engineering and Computer Science Department, University of California, Berkeley, Berkeley, CA
pp. 27-33

Semantics of CAD Objects for Generalized Databases (PDF)

D. Rieu , IMAG Universite de Grenoble Laboratoire de Genie Informatique, St-MARTIN-D'HERES, France
pp. 34-40

DOSS: A Storage System for Design Data (PDF)

S. Weiss , Microelectronics and Computer Technology Corporation, Austin, TX
pp. 41-47

A Design Utility Manager: the ADAM Planning Engine (PDF)

D.W. Knapp , University of Southern California Department of Electrical Engineering
pp. 48-54

VLSI CAD Tool Integration Using the Ulysses Environment (PDF)

M.L. Bushnell , SRC-CMU Research Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 55-61

An Expert-System Paradigm for Design (PDF)

F.D. Brewer , Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 62-68

Tutorial on Parallel Processing for Design Automation Applications (PDF)

J.M. Hancock , International Business Machines Corporation, Poughkeepsie, NY
pp. 69-77

MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators (PDF)

T. Sasao , Department of Electronic Engineering, Osaka University, Suita, Japan
pp. 86-93

Technology Adaptation in Logic Synthesis (PDF)

W.H. Joyner , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 94-100

A New Algorithm for Floorplan Design (PDF)

D.F. Wong , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 101-107

Two-Dimensional Compaction by 'Zone Refining' (PDF)

Hyunchul Shin , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 115-122

Minplex - A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout (PDF)

S.L. Lin , Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
pp. 123-130

GEMS: An Automatic Layout Tool for MIMOLA Schematics (PDF)

V.V. Venkataraman , Honeywell Computer Sciences Center, North Golden Valley, MN
pp. 131-137

An Object-Oriented Visual Simulator for Microprogram Development (PDF)

A. Sugimoto , Central Research Laboratory, Mitsubishi Elec. Corp., AMAGASAKI, Japan
pp. 138-144

A Monitor for Complex CAD Systems (PDF)

A. Di Janni , CSELT - Centro Studi E Laboratori Telecomunicazioni, Torino, Italy
pp. 145-151

Automating the Generation of Interactive Interfaces (PDF)

K. Hammer , Systems Technology Laboratory, VLSI CAD Program, Microelectronics and Computer Technology Corporation
pp. 152-158

SIMMOS: A Multiple-Delay Switch-Level Simulator (PDF)

D. Adler , Motorola Semiconductor Israel (MSIL), Ramat-Gan, Israel
pp. 159-163

MOS Circuit Models in Network C (PDF)

W.S. Beckett , UW/NW VLSI Consortium Department of Computer Science, University of Washington
pp. 171-178

CINNAMON: Coupled Integration and Nodal Analysis of MOS Networks (PDF)

L.M. Vidigal , SRC-CMU Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 179-185

A Workstation-Based Mixed Mode Circuit Simulator (PDF)

P. Odryna , Silicon Design Labs, Liberty Corner, NJ
pp. 186-192

Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs (PDF)

Y.S. Kuo , Institute of Information Science, Academia Sinica, Taipei, Taiwan, The Republic of China
pp. 193-199

A New Method for Verifying Sequential Circuits (PDF)

K.J. Supowit , Department of Computer Science, Princeton University, Princeton, NJ
pp. 200-207

A Logic Verifier Based on Boolean Comparison (PDF)

G. Odawara , Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Tokyo, JAPAN
pp. 208-214

Reasoning about Digital Systems Using Temporal Logic (PDF)

S. Bapat , Dept. of Computer Sc. & Engg., Indian Institute of Technology
pp. 215-219

SCAT - A New Statistical Timing Verifier in a Silicon Compiler System (PDF)

M. Glesner , Technical University Darmstadt, Darmstadt, FR Germany, Institut fuer Halbleitertechnik
pp. 220-226

An Accurate Delay Modeling Technique for Switch-Level Timing Verification (PDF)

S.H. Hwang , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 227-233

Yield of VLSI Circuits: Myths vs. Reality (PDF)

A.J. Strojwas , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 234-235

Robust Test Generation Algorithm for Stuck-Open Fault in CMOS Circuits (PDF)

Mao Weiwei , Electronic Engineering Department, Fudan University, Shanghai, People's Republic of China
pp. 236-242

Transistor-Level Test Generation for Physical Failures in CMOS Circuits (PDF)

Hsi-Ching Shih , Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL
pp. 243-249

A Heuristic Chip-Level Test Generation Algorithm (PDF)

D.S. Barclay , Electrical Engineering Department, Virginia Tech, Blacksburg, VA
pp. 257-262

A New Synthesis Algorithm for the MIMOLA Software System (PDF)

P. Marwedel , Institut fur Informatik und Prakt. Math., University of Kiel, Kiel, W. Germany
pp. 271-277

Synthesis of VLSI Systems with the CAMAD Design Aid (PDF)

Z. Peng , Department of Computer and Information Science, Linkoping University, Linkoping, Sweden
pp. 278-284

Synthesis of Concurrent Modular Controllers from Algorithmic Descriptions (PDF)

R. Bruck , Universitat Dortmund, FB Informatik I, Dortmund, W. Germany
pp. 285-292

Integrated Placement/Routing in Sliced Layouts (PDF)

A.A. Szepieniec , Tangent Systems Corporation, Santa Clara
pp. 300-307

On the Relative Placement and the Transportation Problem for Standard-Cell Layout (PDF)

K.M. Just , Institute of Computer-Aided Design, Department of Electrical Engineering, Technical University of Munich
pp. 308-313

Analysis of Placement Procedures for VLSI Standard Cell Layout (PDF)

M.R. Hartoog , VLSI Technology, Inc., San Jose, CA
pp. 314-319

An Overview of VHDL Language and Technology (PDF)

M. Shahdad , CAD Language Systems, Inc., Potomac, MD
pp. 320-326

A Unified Treatment of PLA Faults by Boolean Differences (PDF)

W. Daehn , Institut fur Theoretische Elektrotechnik, Universitat Hannover, Hannover, West Germany
pp. 334-338

Design-for-Testability of PLA'S Using Statistical Cooling (PDF)

M.M. Ligthart , Philips Research Laboratories, Eindhoven, the Netherlands
pp. 339-345

Use of the Supscripted DALG in Submodule Testing with Applications in Cellular Arrays (PDF)

M. Ladjadj , Rensselaer Polytechnic Institute Center for Integrated Electronics, Troy, NY
pp. 346-353

Self-Testing with Correlated Faults (PDF)

D.R. Tryon , International Business Machines Corporation, Tokyo System Evaluation Laboratory, Tokyo, Japan
pp. 374-377

Automatic Generation of Self-Test Programs - A New Feature of the MIMOLA Design System (PDF)

G. Kruger , Institut fur Informatik u. Prakt. Math., Universitat Kiel, Kiel, W. Germany
pp. 378-384

Efficient Spare Allocation in Reconfigurable Arrays (PDF)

Sy-Yen Kuo , Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana, IL
pp. 385-390

Incremental Logic Synthesis through Gate Logic Structure Identification (PDF)

T. Shinsha , Systems Development Laboratory, Hitachi, Ltd., Kawasaki-shi, Japan
pp. 391-397

A Time and Space Efficient Net Extractor (PDF)

S. Nahar , University of Minnesota
pp. 411-417

A Technology Independent Approach to Hierarchical IC Layout Extraction (PDF)

A. Bootehsaz , Department of Electrical Engineering and Electronics, University of Manchester Institute of Science and Technology, Manchester, England.
pp. 425-431

TimberWolf3.2: A New Standard Cell Placement and Global Routing Package (PDF)

C. Sechen , Department of EECS, University of California, Berkeley, CA
pp. 432-439

Vanguard: A Chip Physical Design System (PDF)

P.S. Hauge , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 440-446

Automated Layout Synthesis in the YASC Silicon Compiler (PDF)

D.E. Krekelberg , Advanced ECAD Laboratory, Control Data Corporation, Minneapolis, MN
pp. 447-453

SEHWA: A Program for Synthesis of Pipelines (PDF)

Nohbyung Park , Department of Electrical Engineering-Systems, University of Southern California, University Park, Los Angeles, CA
pp. 454-460

MAHA: A Program for Datapath Synthesis (PDF)

A.C. Parker , Department of Electrical Engineering-Systems, University of Southern California
pp. 461-466

PLEST: A Program for Area Estimation of VLSI Integrated Circuits (PDF)

F.J. Kurdahi , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 467-473

Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions (PDF)

M.C. McFarland , AT&T Bell Laboratories, Murray Hill, N.J. and Dept. of Computer Science, Boston College, Chestnut Hill, MA
pp. 474-480

Hierarchical Global Wiring for Custom Chip Design (PDF)

W.K. Luk , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 481-489

An Industrial World Channel Router for Non-Rectangular Channels (PDF)

C.H. Ng , VLSI Technology, Inc., San Jose, CA
pp. 490-494

Chameleon: A New Multi-Layer Channel Router (PDF)

D. Braun , Department of Electrical Engineering and Computer Sciences, Electronics Research Laboratory, University of California, Berkeley, CA
pp. 495-502

Flow Graph Representation (PDF)

A. Orailoglu , Gould Research Center, Rolling Meadows, IL
pp. 503-509

A Design Rule Database System to Support Technology-Adaptable Applications (PDF)

J.S. Aude , Department of Computer Science, University of Manchester, Manchester, UK
pp. 510-516

STL - A High Level Language for Simulation and Test (PDF)

J. Ivie , SDA Systems, Santa Clara, CA
pp. 517-523

GENERIC: A Silicon Compiler Support Language (PDF)

J.A. Solworth , Department of Computer Science, Cornell University, Ithaca, NY
pp. 524-530

Knowledge-Based Expert Systems and Their Application (PDF)

W. Birmingham , Trimeter Technologies Corporation, Pittsburgh, PA
pp. 531-539

On Fault Modeling for Dynamic MOS Circuits (PDF)

H.-J. Wunderlich , University of Karlsruhe Institut fuer Informatik, Karlsruhe, F. R. Germany
pp. 540-546

Effectiveness of Heuristics Measures for Automatic Test Pattern Generation (PDF)

S. Patel , International Business Machines Corporation, Poughkeepsie, NY
pp. 547-552

Mixed-Level Fault Coverage Estimation (PDF)

Hi Keung Ma , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 553-559

Optimal Order of the VLSI IC Testing Sequence (PDF)

W. Maly , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 560-566

Multiprocessor-Based Placement by Simulated Annealing (PDF)

S.A. Kravitz , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 567-573

A New Routing Algorithm and Its Hardware Implementation (PDF)

T. Watanabe , NTT Electrical Communications Laboratories, Kanagawa, Japan
pp. 574-580

An Empirical Analysis of the Performance of a Multiprocessor-Based Circuit Simulator (PDF)

G.K. Jacob , Department of Electrical Engineering and Computer Sciences, Electronics Research Laboratory, University of California, Berkeley, CA
pp. 588-593

Flute - A Floorplanning Agent for Full Custom VLSI Design (PDF)

H. Watanabe , AT&T Bell Laboratories, Holmdel, NJ
pp. 601-607

PEARL: An Expert System for Power Supply Layout (PDF)

E.J. DeJesus , DIGITAL EQUIPMENT CORPORATION CAD Systems Engineering, Andover, MA
pp. 615-621

Automatic Placement A Review of Current Techniques (PDF)

B.T. Preas , Xerox Palo Alto Research Center, Palo Alto, CA
pp. 622-629

Panel: Floor Planning Systems (PDF)

H.S. Rifkin , RCA Microelectronics Center, Somerville, NJ
pp. 630

GENIE: A Generalized Array Optimizer for VLSI Synthesis (PDF)

S. Devadas , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 631-637

Comparisons of CMOS PLA and Polycell Representations of Control Logic (PDF)

C.M. Gerveshi , AT&T Bell Laboratories, Murray Hill, NJ
pp. 638-642

An Implementation of a State Assignment Heuristic (PDF)

A.J. Coppola , Intel Corporation, Hillsboro, OR
pp. 643-649

Escher--A Geometrical Layout System for Recursively Defined Circuits (PDF)

E. Clarke , Department of Computer Science, Carnegie-Mellon University, Pittsburgh
pp. 650-653

MADMACS: A New VLSI Layout Macro Editor (PDF)

P. Frison , IRISA - Campus de Beaulieu, RENNES CEDEX - FRANCE
pp. 654-658

Dual Quadtree Representation for VLSI Designs (PDF)

S.K. Nandy , Department of Computer Science, State University of New York at Stony Brook, Stony Brook, NY
pp. 663-666

Precedent-Based Manipulation of VLSI Structures (PDF)

R.H. Lathrop , MIT Artificial Intelligence Laboratory, Cambridge, MA
pp. 667-670

A Rule-Based Approach to Unifying Functional and Fault Simulation and Timing Verification (PDF)

S. Ghosh , Computer Systems Laboratory, Stanford University, Stanford, CA
pp. 677-682

Plug-In Timing Models for an Abstract Timing Verifier (PDF)

D.E. Wallace , Computer Science Division Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 683-689

Delay Reduction Using Simulated Annealing (PDF)

J.D. Pincus , Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA
pp. 690-695

A New Approach to Multi-Layer PCB Routing with Short Vias (PDF)

J.F. Naveda , Computer Science Department, University of Minnesota, Minneapolis, MN
pp. 696-701

A Preprocessor for the Via Minimization Problem (PDF)

K.C. Chang , Department of Computer Science, University of Minnesota, Minneapolis, MN
pp. 702-707

Near-Optimal n-Layer Channel Routing (PDF)

R.J. Enbody , Dept. of Computer Science, University of Minnesota, Minneapolis, MN
pp. 708-714

Principles of the SYCO Compiler (PDF)

A. Jerraya , IMAG/TIM3, GRENOBLE, FRANCE
pp. 715-721

DATAPATH: A CMOS Data Path Silicon Assembler (PDF)

T. Marshburn , Hewlett-Packard, Cupertino IC Division, Cupertino, CA
pp. 722-729

An Intelligent Module Generator Environment (PDF)

P. Six , VSDM division of IMEC, Heverlee, Belgium
pp. 730-735

HAPPI: A Chip Compiler Based on Double-Level-Metal Technology (PDF)

R. Putatunda , RCA/Aerospace and Defense/Advanced Technology Laboratories, Moorestown, NJ
pp. 736-743

An Object-Oriented, Procedural Database for VLSI Chip Planning (PDF)

W. Wolf , AT&T Bell Laboratories, Murray Hill, NJ
pp. 744-751

An Automated Database Design Tool Using the ELKA Conceptual Model (PDF)

J. Gonzalez-Sustaeta , Instituto de Investigaciones Electricas, Cuernavaca, Mor., Mexico
pp. 752-759

A Database Interface for an Integrated CAD System (PDF)

C. Jullien , Centre National d'Etudes des Telecommunications, MEYLAN, FRANCE
pp. 760-767

Rules-Based Object Clustering: A Data Structure for Symbolic VLSI Synthesis and Analysis (PDF)

R.P. Larsen , Semiconductor Products Division, Rockwell International Corporation, Newport Beach, CA
pp. 768-777

Simulating and Controlling the Effects of Transmission Line Impedance Mismatches (PDF)

R.E. Canright , Martin Marietta Orlando Aerospace, Orlando, FL
pp. 778-785

A Delay Test System for High Speed Logic LSI's (PDF)

K. Kishida , Device Development Center, Hitachi Ltd., Tokyo, JAPAN
pp. 786-790

Router System for Printed Wiring Boards of Very High-Speed, Very Large-Scale Computers (PDF)

T. Tada , DA Development Department, Fujitsu Limited, Kawasaki, Japan
pp. 791-797

Global Forced Hierarchical Router (PDF)

J. Kessenich , Hewlett-Packard Company
pp. 798-802

Hierarchical Dynamic Router (PDF)

K. Kawamura , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 803-809

A Parameter-Driven Router (PDF)

V.S. Bobba , Department of Computer Science, The University of Georgia
pp. 810-818

Early Verification of Prototype Tooling for IC Designs (PDF)

P. Lamey , KLA INSTRUMENTS CORPORATION
pp. 819-822

Algorithms for Global Routing (PDF)

J.G. Xiong , Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA
pp. 824-830

Reviewers (PDF)

pp. 831,832
87 ms
(Ver 3.3 (11022016))