The Community for Technology Leaders
Design Automation Conference (1985)
Las Vegas, Nevada, USA USA
June 23, 1985 to June 26, 1985
ISSN: 0738-100X
ISBN: 0-8186-0635-5
TABLE OF CONTENTS

Towards a Natural Language Interface for CAD (PDF)

T. Samad , Department of Electrical and Computer Engineering, Carnegie-Mellon University
pp. 2-8

Unified User Interface for a CAD System (PDF)

A. Di Janni , CSELT - Centro Studi E Laboratori Telecomunicazioni, Torino, Italy
pp. 9-15

A Design by Example Regular Strcture Generator (PDF)

C.S. Bamji , Research Laboratory of Electronics and Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
pp. 16-22

A Technique for Distributed Execution of Design Automation Tools (PDF)

S.C. Hughes , International Business Machines Corporation, Data Systems Division, Kingston, NY
pp. 23-30

ACORN: A Local Customization Approach to DCVS Physical Design (PDF)

E.J. Yoffa , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 32-38

Systematic and Optimized Layout of MOS Cells (PDF)

G. Saucier , Laboratoire "Circuits et systemes" - Institut IMAG, SAINT MARTIN D'HERES CEDEX, FRANCE
pp. 53-61

MCNC's Vertically Integrated Symbolic Design System (PDF)

C.D. Rogers , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 63-68

A Fully Automatic Hierarchical Compactor (PDF)

G. Entenman , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 69-75

The VIVID System Approach to Technology Independence: the Master Technology File System (PDF)

P. Smith , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 76-81

Auto-interactive Schematics to Layout Translation (PDF)

J.B. Rosenberg , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 82-87

Importance of Standards (PDF)

A. Lowenstein , Prospective Computer Analysts, Inc., Roslyn, NY
pp. 88-93

Mechanical Design/Analysis Integration on Apollo Workstations (PDF)

J.A. Pierro , Honeywell Electro-Optics Division, Lexington, MA
pp. 96-101

Custom Microcomputers for CAD Optimization Software (PDF)

R. Abraham , General Motors/ Electronic Data Systems Corporation
pp. 102-110

A Database Management Approach to CAD/CAM Systems Integration (PDF)

Y.E. Kalay , School of Architecture and Environmental Design, State University of New York, Buffalo, NY
pp. 111-116

Two-Dimensional Router for Double Layer Layout (PDF)

M. Marek-Sadowska , Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA
pp. 117-123

Timing Influenced Layout Design (PDF)

M. Burstein , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 124-130

An Algorithm for One and Half Layer Channel Routing (PDF)

J.N. Song , Department of Electrical Engineering, Tsinghua University, Beijing, China
pp. 131-136

Macromodeling of Digital MOS VLSI Circuits (PDF)

M.D. Matson , Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
pp. 144-151

ACTAS: An Accurate Timing Analysis System for VLSI (PDF)

M. Muraoka , OKI Electric Industry Company, Ltd., Tokyo, JAPAN
pp. 152-158

Decomposition of Logic Networks into Silicon (PDF)

S.T. Healey , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 162-168

SWAMI: A Flexible Logic Implementation System (PDF)

C. Rowen , Computer Systems Laboratory, Stanford University, Stanford CA
pp. 169-175

Yet Another Silicon Compiler (PDF)

D.E. Krekelberg , Advanced ECAD Department Control Data Corporation, Minneapolis, MN
pp. 176-182

ALLENDE: A Procedural Language for the Hierarchical Specification of VLSI Layouts (PDF)

J.M. da Mata , Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ and Departamento de Ciencia da Computacao, Universidade Federal de Minas Gerais, Belo Horizonte, MG, BRASIL
pp. 183-189

Design for Testability in a Silicon Compilation Environment (PDF)

H.S. Fung , GTE Laboratories Incorporated, Waltham, MA
pp. 190-196

PLATYPUS: A PLA Test Pattern Generation Tool (PDF)

Ruey-Sing Wei , Department of EECS, University of California, Berkeley, Berkeley, CA
pp. 197-203

PROTEST: A Tool for Probabilistic Testability Analysis (PDF)

H.-J. Wunderlich , Universitat Karlsruhe Institut fur Informatik IV, Karlsruhe, Federal Republic of Germany
pp. 204-211

Workstations: A Complete Solution to the VLSI Designer? (PDF)

P. Agrawal , AT&T Bell Laboratories, Murray Hill, NJ
pp. 219

Workstations: A Complete Solution to the VLSI Designer? (PDF)

F.L. Cohen , Mentor Graphics Corporation, Beaverton, OR
pp. 220

Workstations: A Complete Solution to the VLSI Designer? (PDF)

H.S. Law , SDA Systems, Santa Clara, CA
pp. 221

Workstations: A Complete Solution to the VLSI Designer? (PDF)

M. Miller , Daisy Systems Corporation, Mountain View, CA
pp. 222

Workstations: A Complete Solution to the VLSI Designer? (PDF)

M. Price , Valid Logic Systems, Inc., San Jose, CA
pp. 223

Workstations: A Complete Solution to the VLSI Designer? (PDF)

D.W. Smith , Metheus-Computer Vision, Inc., Hillsboro, OR
pp. 224

Workstations: A Complete Solution to the VLSI Designer? (PDF)

N.P. Brunt , Research & Development, Zycad Corporation, Arden Hills, MN
pp. 225

Course, Video, and Manual Dexterity: Tailoring Training to CAD Users (PDF)

F.S. Frome , AT&T Bell Laboratories, Murray Hill, NJ
pp. 226-231

A Functional Language for Description and Design of Digital Systems: Sequential Constructs (PDF)

F. Meshkinpour , Computer Science Department, University of California at Los Angeles, Los Angeles, CA
pp. 238-244

Layla: A VLSI Layout Language (PDF)

W.E. Cory , Silvar-Lisco, Menlo Park, CA
pp. 245-251

A Knowledge Based System for Selecting a Test Methodology for a PLA (PDF)

M.A. Breuer , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 259-265

WEAVER: A Knowledge-Based Routing Expert (PDF)

R. Joobbani , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 266-272

Generalised CMOS - A Technology Independent CMOS IC Design Style (PDF)

N. Bergmann , Department of Computer Science, University of Edinburgh, Edinburgh, SCOTLAND
pp. 273-278

Technology Tracking for VLSI Layout Design Tools (PDF)

Kung-Chao Chu , Microelectronics and Computer Technology Corporation (MCC), Austin, TX
pp. 279-285

Magic's Circuit Extractor (PDF)

W.S. Scott , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 286-292

Hierarchical Analysis of IC Artwork with User Defined Abstraction Rules (PDF)

L.K. Scheffer , Valid Logic Systems, Incorporated, San Jose, CA
pp. 293-298

An Algorithm for Design Rule Checking on a Multiprocessor (PDF)

G.E. Bier , The University of Wisconsin-Madison Computer Sciences Department, Madison, WI
pp. 299-304

Resistance Calculation from Mask Artwork Data by Finite Element Method (PDF)

E. Barke , Department of Electrical Engineering, University of Hannover, Germany FR
pp. 305-311

A Data Architecture for an Uncertain Design and Manufacturing Environment (PDF)

T.R. Smith , DIGITAL EQUIPMENT CORPORATION, Andover, MA
pp. 312-318

CMU-CAM System (PDF)

A.J. Strojwas , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 319-325

Cost-Effective Computer-Aided Manufacturing of Prototype Parts (PDF)

K.S. Reid-Green , RCA David Sarnoff Research Center, Princeton, NJ
pp. 326-329

A Knowledge Based Planning System for Mechanical Assembly Using Robots (PDF)

Kai-Hsiung Chang , Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH
pp. 330-336

Layout Design--Lessons from the Jedi Designer (PDF)

S.L. Taylor , AT&T Bell Laboratories, Murray Hill, NJ
pp. 337

MuSiC An Event-Flow Computer for Fast Simulation of Digital Systems (PDF)

W. Hahn , University of Passau, Department of Computer Science, Passau, F.R. Germany
pp. 338-344

A Hardware Engine for Analogue Mode Simulation of MOS Digital Circuits (PDF)

D.M. Lewis , Computer Systems Research Institute, University of Toronto, Canada
pp. 345-351

Hardware Acceleration of Gate Array Layout (PDF)

P.M. Spira , Daisy Systems Corporation, Mountain View, CA
pp. 359-366

Synthesis by Delayed Binding of Decisions (PDF)

J.V. Rajan , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 367-373

Linking the Behavioral and Structural Domains of Representation in a Synthesis System (PDF)

R.L. Blackburn , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 374-380

An Automated Data Path Synthesizer for a Canonic Structure, Implementable in VLSI (PDF)

K. Ramayya , Department of Electrical Engineering, Indian Institute of Technology, Delhi, India
pp. 381-387

Automatic Generation of Digital System Schematic Diagrams (PDF)

A. Arya , Elec. Engg. Deptt., Indian Institute of Technology, New Delhi, INDIA
pp. 388-395

A Subjective Review of Compaction (PDF)

Y.E. Cho , CALMA Company, Electronics R&D, Milpitas, CA
pp. 396-404

Looking for Mr. "Turnkey" (PDF)

M.R. Wayne , International Business Machines Corporation, Poughkeepsie, NY
pp. 405-409

An Architecture Design and Assessment System for Software/Hardware Codesign (PDF)

C.U. Smith , Department of Computer Science, Duke University, Durham, NC
pp. 417-424

Yield Analysis Modeling (PDF)

S. Perry , NCA Corporation, Santa Clara, CA
pp. 425-428

A Circuit Comparison System for Bipolar Linear LSI (PDF)

T. Sakata , Second LSI Division, NEC Corporation, Kawasaki, Japan
pp. 429-434

Silicon Compilation of Gate Array Bases (PDF)

R.L. Steinweg , VLSI Technology, Inc., San Jose, CA
pp. 435-438

A Hierarchical Gate Array Architecture and Design Methodology (PDF)

M. Iacoponi , Harris Corporation, Government Aerospace Systems Division, Melbourne, FL
pp. 439-442

Plint Layout System for VLSI Chips (PDF)

H. Anway , General Electric Aerospace Electronic Systems Department, Utica, NY
pp. 449-452

A Model of Design Representation and Synthesis (PDF)

R.A. Walker , Electrical and Computer Engineering Dept., Carnegie-Mellon University, Pittsburgh, PA
pp. 453-459

A Behavioral Modeling System for Cell Compilers (PDF)

J.C. Althoff , VLSI Technology, Inc., San Jose, CA
pp. 468-474

Synthesis Techniques for Digital Systems Design (PDF)

R. Camposano , Universitat Karlsruhe Forschungszentrum Informatik, Karlsruhe F.R.Germany
pp. 475-481

Synthesis of Optimal Clocking Schemes (PDF)

Nohbyung Park , Department of Electrical Engneering - Systems, University of Southern California, Los Angeles, CA
pp. 489-495

Future Directions for DA Machine Research (PDF)

R.A. Rutenbar , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 496-497

The Impact of Technological Advances on Programmable Controllers (PDF)

R.P. Collins , General Electric Company, Automations Controls Department, Charlottesville, VA
pp. 498-502

A Routing Procedure for Mixed Array of Custom Macros and Standard Cells (PDF)

H. Terai , Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan
pp. 503-508

A Method for Gridless Routing of Printed Circuit Boards (PDF)

A.C. Finch , Racal-Redac Ltd., Newtown, Tewkesbury, Glos., England
pp. 509-515

MIDAS: Integrated CAD for Total System Design (PDF)

W.M. Budney , Control Data Corporation, Bloomington, MN
pp. 529-535

Integrated Design System for Supercomputer SX-1/SX-2 (PDF)

S. Suzuki , NEC Corporation, Fuchu City, Tokyo, Japan
pp. 536-542

Integrated VLSI CAD Systems at Digital Equipment Corporation (PDF)

A.F. Hutchings , Digital Equipment Corporation, Hudson, MA
pp. 543-548

Computer Aided Design for Analog Applications: An Assessment (PDF)

J. Lowell , United Technologies Mostek, Carrollton, TX
pp. 554

Tutorial: Software Quality Assurance for CAD (PDF)

E.T. Grinthal , AT&T Bell Laboratories, Murray Hill, NJ
pp. 555-561

Development Concerns for a Software Design Quality Expert System (PDF)

C.W. Pidgeon , REUSE Project, University of California, Irvine
pp. 562-568

ICHABOD A Data Base Manager for Design Automation Applications (PDF)

H.B. Schutzman , Honeywell Information Systems, Inc., Billerica, MA
pp. 569-576

A Case Study in Process Independence (PDF)

N. Royal , Lattice Logic Ltd, Edinburgh, Scotland
pp. 591-596

Portability in Silicon CAE (PDF)

J.P. Gray , Lattice Logic Ltd, Edinburgh, UK
pp. 597-601

An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks (PDF)

Lu Sha , Stanford Electronics Laboratory, Stanford University, Stanford, CA
pp. 602-608

Near-Optimal Placement Using a Quadratic Objective Function (PDF)

J.P. Blanks , VR Information Systems, Inc., Austin, TX
pp. 609-615

Knowledge-Based Placement Technique for Printed Wiring Boards (PDF)

G. Odawara , Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Tokyo, Japan
pp. 616-622

An Object-Oriented Switch-Level Simulator (PDF)

C. Roy , Dept. d'informatique et de recherche operationnelle Universite de Montreal, Montreal, Canada
pp. 623-629

An Extensible Object-Oriented Mixed-Mode Functional Simulation System (PDF)

R.H. Lathrop , M.I.T. Artificial Intelligence Laboratory, Cambridge, MA
pp. 630-636

Modeling Switch-Level Simulation Using Data Flow (PDF)

V. Ashok , Department of Computer and Information Science, The Ohio State University, Columbus, OH
pp. 637-644

Building A Layered Database for Design Automation (PDF)

R.V. Zara , CAE Systems, a Division of Tektronix, Inc., Sunnyvale, CA
pp. 645-651

Effective Data Management for VLSI Design (PDF)

P. McLellan , VLSI Technology, Inc., San Jose, CA
pp. 652-657

CADTOOLS: A CAD Algorithm Development System (PDF)

E. Schell , Calma Company, Austin, TX
pp. 658-666

The McBoole Logic Minimizer (PDF)

M.R. Dagenais , Department of Electrical Engineering, McGill University, Montreal
pp. 667-673

Multiple Output Minimization (PDF)

P. Agrawal , AT&T Bell Laboratories, Murray Hill, NJ
pp. 674-680

Electrical Optimization of PLAs (PDF)

K.S. Hedlund , Department of Computer Science, University of North Carolina, Chapel Hill, NC
pp. 681-687

Symbolic Manipulation of Boolean Functions Using a Graphical Representation (PDF)

R.E. Bryant , Carnegie-Mellon University, Dept. of Computer Science, Pittsburgh, PA
pp. 688-694

Hierarchical Circuit Verification (PDF)

Yiwan Wong , Department of Computer Science, Yale University, New Haven, CT
pp. 695-701

Efficient Netlist Comparison Using Hierarchy and Randomization (PDF)

J.D. Tygar , Aiken Computation Lab., Harvard U., Cambridge, MA
pp. 702-708

Analysis of Timing Failures Due to Random AC Defects in VLSI Modules (PDF)

N.N. Tendolkar , IBM Corporation, Data Systems Division, Poughkeepsie, NY
pp. 709-714

Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator (PDF)

R.E. Bryant , Carnegie-Mellon University, Dept. of Computer Science, Pittsburgh, PA
pp. 715-719

Functional Fault Modeling and Simulation for VLSI Devices (PDF)

A.K. Gupta , Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
pp. 720-726

Diagrammatic Functional Description of Microprocessor and Data-Flow Processor (PDF)

G. Odawara , Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Tokyo, JAPAN
pp. 731-734

Switch-Level Simulation of VLSI Using a Special-Purpose Data-Driven Computer (PDF)

E.H. Frank , Carnegie-Mellon University, Department of Computer Science, Pittsburgh, PA
pp. 735-738

PHIPLA--A New Algorithm for Logic Minimization (PDF)

P.J.M. van Laarhoven , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 739-743

A Heuristic Algorithm for PLA Block Folding (PDF)

Y.S. Kuo , Institute of Information Science, Academia Sinica, Taipei, Taiwan, Republic of China
pp. 744-747

Experiments with Simulated Annealing (PDF)

S. Nahar , University of Minnesota
pp. 748-752

An Abstract Machine Data Structure For Non-Procedural Functional Models (PDF)

R.V. Zara , CAE Systems, a Division of Tektronix, Inc., Sunnyvale, CA
pp. 753-756

A Transistor-Level Logic-with-Timing Simulator for MOS Circuits (PDF)

T.J. Schaefer , VLSI Technology, Inc., San Jose, CA
pp. 762-765

PLAYER: A PLA Design System For VLSI's (PDF)

Y. Koseki , NEC Corporation, Kawasaki, JAPAN
pp. 766-769

GAMMA A Fast Prototype Design, Build, and Test Process (PDF)

L.T. Lemaire , DIGITAL EQUIPMENT CORPORATION, Andover, MA
pp. 773-776

Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits (PDF)

W.H. Kao , Xerox Corporation, Electronics Division, El Segundo, CA
pp. 781-784

Automatic Routing Algorithm for VLSI (PDF)

H. Andou , OKI Electric Industry Co., Ltd., Tokyo, JAPAN
pp. 785-788

The Construction of Minimal Area Power and Ground Nets for VLSI Circuits (PDF)

S. Chowdhury , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 794-797

PLA Driver Selection: An Analytic Approach (PDF)

F.W. Obermeier , Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA
pp. 798-802

RTG: Automatic Register Level Test Generator (PDF)

S. Shteingart , AT&T Bell Laboratories, Summit, NJ
pp. 803-807

Simulation-Free Estimation of Speed Degradation in NMOS Self-Testing Circuits for CAD Applications (PDF)

A. Krasniewski , Department of Electrical Engineering, The University of Rochester, Rochester, NJ
pp. 808-811

Speed up Techniques of Logic Simulation (PDF)

M. Miyoshi , Kanagawa Works, Hitachi, Ltd., Kanagawa, Japan
pp. 812-815

Development of a Timing Analysis Program for Multiple Clocked Network (PDF)

E. Chan , National Semiconductor, Santa Clara, CA
pp. 816-819

Transistor Level Test Generation for MOS Circuits (PDF)

M.K. Reddy , Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa
pp. 825-828

Electronic CAD/CAM - Is It Revolution or Evolution (PDF)

B.W. Tucker , Dataquest Incorporated, San Jose, CA
pp. 830-834
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