The Community for Technology Leaders
Design Automation Conference (1984)
Albuquerque, NM, USA USA
June 25, 1984 to June 27, 1984
ISSN: 0738-100X
ISBN: 0-8186-0542-1
TABLE OF CONTENTS

The Second Generation MOTIS Mixed-Mode Simulator (PDF)

C.F. Chen , AT$#x0026;T Bell Laboratories, Murray Hill, NJ
pp. 10-17

STAFAN: An Alternative to Fault Simulation (PDF)

S.K. Jain , AT$#x0026;T Bell Laboratories, Murray Hill, NJ
pp. 18-23

A Wire Routing Scheme for Double-Layer Cell Arrays (PDF)

G. Dupenloup , IMAG, Laboratoire de Genie Informatique, Saint-Martin d'Heres CEDEX, France
pp. 32-37

An Efficient Channel Router (PDF)

T. Yoshimura , NEC Corporation, Kawasaki, JAPAN
pp. 38-44

A Global Routing Algorithm for General Cells (PDF)

G.W. Clow , Department of Computer Science, California Institute of Technology, Pasadena, CA
pp. 45-51

A Symbolic-Interconnect Router for Custom IC Design (PDF)

C.H. Ng , VLSI Technology, Inc., San Jose, CA
pp. 52-58

HARPA: A Hierarchical Multi-Level Hardware Description Language (PDF)

P.M.B. Veiga , Departamento de Engenharia Electrotecnica, Instituto Superior Tecnico, LISBOA, PORTUGAL
pp. 59-65

ADL: An Algorithmic Design Language for Integrated Circuit Synthesis (PDF)

W.H. Evans , Laboratoire Central de Recherches, Thomson-CSF, Orsay Cedex, France
pp. 66-72

A Symbolic Functional Description Language (PDF)

G. Odawara , Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Tokyo, Japan
pp. 73-80

Silicon Compilers and Expert Systems for VLSI (PDF)

D.D. Gajski , Department of Computer Science, University of Illinois at Urbana-Champaign
pp. 86-87

A Technology Independent MOS Multiplier Generator (PDF)

Kung-chao Chu , Bell Laboratories, Murray Hill, NJ
pp. 90-97

The Icewater Language and Interpreter (PDF)

P.A.D. Powell , VLSI Research Group, Institute for Computer Research, University of Waterloo, Waterloo, Ontario, Canada
pp. 98-102

Cell Compilation with Constraints (PDF)

C. Lursinsap , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 103-108

Extending the Relational Database Data Model for Design Applications (PDF)

M. Hardwick , Department of Electrical Engineering/Computer Science, Texas Tech University, Lubbock, TX
pp. 110-116

A Hiererachical, Error-Tolerant Compactor (PDF)

C. Kingsley , VLSI Technology, Inc., San Jose, CA
pp. 126-132

Interactive Compaction Router for VLSI Layout (PDF)

H. Mori , C & C Systems Research Laboratories, NEC Corporation, Kawasaki, JAPAN
pp. 137-143

Computer Aided Design (CAD) Using Logic Programming (PDF)

P.W. Horstmann , IBM Corporation General Technology Division
pp. 144-151

Magic: A VLSI Layout System (PDF)

J.K. Ousterhout , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 152-159

Magic's Incremental Design-Rule Checker (PDF)

G.S. Taylor , Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA
pp. 160-165

Plowing: Interactive Stretching and Compaction in Magic (PDF)

W.S. Scott , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 166-172

A Switchbox Router with Obstacle Avoidance (PDF)

G.T. Hamachi , Computer Science Division, Electrical Engineering and Computer Sciences, University of California Berkeley, Berkeley, CA
pp. 173-179

Test Generation for LSI: A Case Study (PDF)

M.S. Abadir , Department of Electrical Engineering, University of Southern California
pp. 180-195

An Approach to the Testing of Microprocessors (PDF)

M.G. Karpovsky , College of Engineering, Boston University, Boston, MA
pp. 196-202

An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview (PDF)

E. Trischler , Siemens Corporate Research and Support, Inc., Research and Technology Laboratories, Princeton, NJ
pp. 209-215

Introduction to the SRC Design Sciences Program (PDF)

R.K. Cavin , Semiconductor Research Corporation, Research Triangle Park, NC
pp. 216-217

Ergonomic Studies in Computer Aided Design (PDF)

G.H. van der Heiden , Swiss Federal Institute of Technology, Department of Ergonomics and Hygiene, Zurich, Switzerland
pp. 220-227

Functional Verification of Memory Circuits from Mask Artwork Data (PDF)

M. Kawamura , TOSHIBA Research and Development Center, Kawasaki, JAPAN
pp. 228-234

The Scan Line Approach to Design Rules Checking: Computational Experiences (PDF)

P.T. Chapman , International Business Machines Corporation, IBM East Fishkill Facility, Hopewell Junction, NY
pp. 235-241

A Systolic Design Rule Checker (PDF)

R. Kane , University of Minnesota
pp. 243-250

A Model for Hardware Description and Verification (PDF)

G.J. Milne , Department of Computer Science, University of Edinburgh, Edinburgh, Scotland
pp. 251-257

A Model for Non Interpreted Structures of Logical Systems (PDF)

R. Alali , Laboratoire d'automatique et de microelectronique de Montpellier Universite des Sciences et Techniques du Languedoc, Montpellier-Cedex, France
pp. 258-264

Towards a Standard Hardware Description Language (PDF)

K.J. Lieberherr , GTE Laboratories Inc., Waltham, MA
pp. 265-272

IGES as an Interchange Format for Integrated Circuit Design (PDF)

C.H. Parks , General Dynamics, Pomona, CA
pp. 273-274

A Designing System for Multi-Family Housing (Abstract)

B. Jackson , School of Architecture, New Jersey Institute of Technology, Newark, NJ
pp. 275-281

Module Design Verification System (PDF)

L. Wilkins , IBM General Technology Division, East Fishkill Hopewell Junction, NY
pp. 282-287

Studying the Mouse for CAD Systems (PDF)

L.A. Price , Calma Company Research $#x0026; Development, Santa Clara, CA
pp. 288-293

AMOEBA: A Symbolic VLSI Layout System (PDF)

M. Lotvin , Honeywell Information Systems, Office Management Systems Division, Billerica, MA
pp. 294-300

ARIES: A Workstation Based, Schematic Driven System for Circuit Design (PDF)

W.H. Kao , XEROX Corporation, Electronics Division, El Segundo, CA
pp. 301-307

A High Level Synthesis Tool for MOS Chip Design (PDF)

J. Dussault , AT&T Bell Laboratories, Murray Hill, NJ
pp. 308-314

Emerald: A Bus Style Designer (PDF)

Chia-Jeng Tseng , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 315-321

POLARIS: Polarity Propagation Algorithm for Combinational Logic Synthesis (PDF)

T. Shinsha , Systems Development Laboratory, Hitachi, Ltd., Kanagawa, Japan
pp. 322-328

A General Methodology for Synthesis and Verification of Register-Transfer Designs (PDF)

A.C. Parker , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, C
pp. 329-335

ULTIMATE: A Hardware Logic Simulation Engine (PDF)

M.E. Glazier , University of Manchester Institute of Science and Technology, Manchester, U.K
pp. 336-342

ORACLE - A Simulator for Bipolar and MOS IC Design (PDF)

M.A. d'Abreu , Honeywell Corporate Solid State Laboratory, Plymouth, MN
pp. 343-349

A Multiprocessor Implementation of Relaxation-Based Electrical Circuit Simulation (Abstract)

J.T. Deutsch , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 350-357

A Unified CAD System for Electronic Design (PDF)

J.C. Foster , AT&T Bell Laboratories, Whippany, NJ
pp. 365-369

Engineering Design Aspects (PDF)

H.Y. Chang , AT&T Bell Laboratories, Naperville, IL
pp. 370-373

Users View (PDF)

J.R. Colton , AT&T Bell Laboratories, Holmdel, NJ
pp. 384

Commercial Gate Array Physical Design Automation Packages (PDF)

F. Hinchliffe , Sanders Associates, Inc., Nashua, NH
pp. 386-387

The Channel Expansion Problem in Layout Design (PDF)

R.R. Chen , Dept. of Elec. Engr., San Jose State University, San Jose, CA
pp. 388-391

A Standard Cell Initial Placement Strategy (PDF)

B.D. Richard , Sandia National Laboratories, Physical CAD Division-2113, Albuquerque, NM
pp. 392-398

Performance of Algorithms for Initial Placement (PDF)

M. Palczewski , Solomon Design Automation Corp., Santa Clara, CA
pp. 399-404

The Rectangle Placement Language (PDF)

J.A. Roach , Department of Computer Science, Hill Center/Busch Campus, Rutgers University, New Brunswick, NJ
pp. 405-411

A Knowledge Based Approach to VLSI CAD the Redesign System (PDF)

L.I. Steinberg , AI/VLSI Project, Department of Computer Science, Rutgers University, New Brunswick, NJ
pp. 412-418

The CRITTER System -- Automated Critiquing of Digital Circuit Designs (PDF)

V.E. Kelly , Department of Computer Science, Rutgers University, New Brunswick, NJ
pp. 419-425

A Branch and Bound Algorithm for Optimal PLA Folding (PDF)

J.L. Lewandowski , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 426-433

A VLSI FSM Design System (PDF)

M.J. Meyer , AT&T Bell Laboratories, Holmdel, NJ
pp. 434-440

Managing A Large Volume of Design/Manufacturing/Test Data in a Chip And Module Factory (PDF)

V.J. Freund , IBM General Technology Division, East Fishkill, Hopewell Junction, NY
pp. 447-451

An Automated System for Testing LSI Memory Chips (PDF)

H.D. Schnurmann , IBM General Technology Division, East Fishkill, Hopewell Junction, NY
pp. 454-458

The Intel Design Automation System (PDF)

S. Nachtsheim , Intel Corporation, Santa Clara, CA
pp. 459-465

The Engineering Design Environment (PDF)

K. Sherhart , Intel Corporation, Santa Clara, CA
pp. 466-472

Performance Verification of Circuits (PDF)

J. Mar , Intel Corporation, Santa Clara, CA
pp. 479-483

Hierarchical Layout Verification (PDF)

T.J. Wagner , Intel Corporation, Santa Clara, CA
pp. 484-489

Taking into Account Asynchronous Signals in Functional Test of Complex Circuits (PDF)

C. Bellon , Laboratoire "Circuits et Systemes" - Institut IMAG, Saint Martin D'heres Cedex - France
pp. 490-496

VLSI Test Expertise System Using a Control Flow Model (PDF)

G. Saucier , Laboratoire "Circuits et Systemes" - Institut IMAG, Saint Martin D'heres Cedex - France
pp. 497-503

A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection (PDF)

S.M. Reddy , Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa
pp. 504-509

Parameterized Random Testing (PDF)

K.J. Lieberherr , GTE Laboratories Incorporated, Waltham, MA
pp. 510-516

Functional Testing Techniques for Digital LSI/VLSI Systems (PDF)

S.Y.H. Su , Department of Computer Science, Thomas J. Watson School of Engineering, Applied Science and Technology, State University of New York, Binghamton, NY
pp. 517-528

Delay and Power Optimization in VLSI Circuits (PDF)

L.A. Glasser , Electrical Engineering and Computer Science Department and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
pp. 529-535

IDA: Interconnect Delay Analysis for Integrated Circuits (PDF)

A.J. de Geus , General Electric Microelectronics Center, Research Triangle Park, NC
pp. 536-541

Switch-Level Delay Models for Digital MOS VLSI (PDF)

J.K. Ousterhout , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 542-548

The VHSIC Hardware Description Language (VHDL) Program (PDF)

A. Dewey , Air Force Wright Aeronautical Laboratories AFWAL/AADE, Wright-Patterson Air Force Base, OH
pp. 556-557

PHLED45: An Enhanced Version of Caesar Supporting 45 ° Geometries (PDF)

A.R. Lanfri , Oregon State University, Corvallis, OR and Metheus Corporation, Hillsboro, OR
pp. 558-564

MICON: A Knowledge Based Single Board Computer Designer (PDF)

W.P. Birmingham , Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
pp. 565-571

MGX: An Integrated Symbolic Layout System for VLSI (PDF)

M. Ozaki , LSI Research and Development Laboratory, Mitsubishi Electric Corporation, Itami, Japan
pp. 572-579

UTMC'S LSI CAD System - HIGHLAND (PDF)

K. Anderson , United Technologies Microelectronics Center, Colorado Springs, CO
pp. 580-586

The MIMOLA Design System: Tools for the Design of Digital Processors (PDF)

P. Marwedel , Institut fur Informatik und Praktische Mathematik, Universitat Kiel, Kiel, W. Germany
pp. 587-593

A Model for University, Industry and Government Cooperation (PDF)

L. Snyder , University of Washington/Northwest VLSI Consortium, Seattle, WA
pp. 602-603

A Technology Independent Block Extraction Algorithm (PDF)

F. Luellau , Department of Electrical Engineering, University of Hannover, Germany FR
pp. 610-615

EXCL: A Circuit Extractor for IC Designs (PDF)

S.P. McCormick , Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
pp. 616-623

An Interactive Electrical Graph Extractor (PDF)

J.L. Kors , Institut de Programmation, Universite PARIS, PARIS
pp. 624-628

Some Consideration on the Data Model of Geometric Data Bases (PDF)

Jinglun Zhang , Manufacturing Department, Beijing Institute of Aeronautics and Astronautics, Beijing, China
pp. 629-633

An Architecture for Application of Artificial Intelligence to Design (PDF)

J.R. Dixon , Knowledge-Based Systems Program, General Electric Corporate Research and Development, Schenectady,NY
pp. 634-640

A Formal Design Verification System Based on an Automated Reasoning System (PDF)

A.S. Wojcik , Department of Computer Science, Illinois Institute of Technology, Chicago, IL
pp. 641-647

The Semi-Custom Revolution: How To Thrive or Survive (PDF)

A. Zingale , Daisy Systems Corporation, Sunnyvale, CA
pp. 649-650

Optimization Techniques for Two-Dimensional Placement (PDF)

L.A. Markov , GTE Laboratories Incorporated, Waltham, MA
pp. 652-654

An Algorithm for Finding a Rectangular Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits (PDF)

K. Kozminski , Department of Electrical Engineering, The University of Rochester, Rochester, NY
pp. 655-656

An Algorithm for Building Rectangular Floor-Plans (PDF)

S.M. Leinwand , University of Illinois, Chicago, Dept. EECS
pp. 663-664

SPIDER, A Chip Planner for ISL Technology (PDF)

P. Rao , Honeywell Computer Science Center, Bloomington, MN
pp. 665-666

Combine and Top Down Block Placement Algorithm for Hierarchical Logic VLSI Layout (PDF)

T. Kozawa , Central Research Laboratory, Hitachi Ltd., Tokyo, JAPAN
pp. 667-669

Initial Placement of Gate Arrays Using Least-Squares Methods (PDF)

J.P. Blanks , VR Information Systems, Inc., Austin, TX
pp. 670-671

Module Positioning Algorithms for Rectilinear Macrocell Assemblies (PDF)

J.A. Hudson , Division 2113, Sandia National Laboratories, Albuquerque, NM
pp. 672-675

Microprocessor Synthesis (PDF)

V.K. Raj , Dept. of Computer Science, University of Illinois, Urbana, IL
pp. 676-678

Topological Routing of Multi-Bit Data Buses (PDF)

G. Persky , Hughes Aircraft Company, Carlsbad, CA
pp. 679-682

An Electronic Design Interchange Format (PDF)

J.D. Crawford , Tektronix, Inc., Beaverton, OR
pp. 683-685

A VLSI Design Methodology Based on Parametric Macro Cells (PDF)

R.A. Kriete , Harris Corporation, Government Systems Sector, Melbourne, FL
pp. 686-688

Methodology for Compiler Generated Silicon Structures (PDF)

A. Martinez , VLSI Technology, Inc., San Jose, CA
pp. 689-691

Design Transaction Management (PDF)

R.H. Katz , Computer Science Division, Electrical Engineering and Computer Science Department, University of California, Berkeley, Berkeley, CA
pp. 692-693

VTIcompose - A Powerful Graphical Chip Assembly Tool (PDF)

S. Trimberger , VLSI Technology, Inc., San, Jose, CA
pp. 697-698

Computer Aided Minimization Procedure for Boolean Functions (PDF)

N.N. Biswas , Indian Institute of Science, Bangalore, India
pp. 699-702

Optimization of Negative Gate Networks Realized in Weinberger-Likf Layout in a Boolean Level Silicon Compiler (PDF)

A. Wieclawski , Warsaw Technical University, Institute of Electron Technology, Warsaw, Nowowiejska, Poland
pp. 703-704

Deadlock Analysis in the Design of Data-Flow Circuits (PDF)

C.S. Jhon , Electrical and Computer Engineering Department, University of Iowa, Iowa City, Iowa
pp. 705-707

A Method for IC Layout Verification (PDF)

O.A. Marvik , Electronics Research Laboratory, University of Trondheim, Trondheim, Norway
pp. 708-709

On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICs (PDF)

S. Sastry , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
pp. 710-711

List of reviewers (PDF)

pp. 713,714
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