The Community for Technology Leaders
Design Automation Conference (1983)
Miami Beach, FL, USA USA
June 27, 1983 to June 29, 1983
ISSN: 0738-100X
ISBN: 0-8186-0026-8
TABLE OF CONTENTS

Central DA and Its Role: An Executive View (PDF)

R.J. Camoin , IBM General Technology Division, East Fishkill Facility, Hopewell Junction, NY
pp. 3

Computer Design Language - Version Munich (CDLM) A Modern Multi-Level Language (PDF)

W. Hahn , University of the Federal Armed Forces, Neubiberg, F.R. Germany
pp. 4-11

Programming Languages for Hardware Description (PDF)

P. Robinson , Cambridge University Computer Laboratory, Cambridge, England
pp. 12-16

ZEUS: A Hardware Description Language for VLSI (PDF)

K.J. Lieberherr , Department of Electrical Engineering and Computer Science Princeton University, Princeton, New Jersey and Institut fur Informatik, ETH Zurich, Zurich, Switzerland
pp. 17-23

Microprocessor Systems Modeling with MODLAN (PDF)

A. Pawlak , Silesian Technical University, Gliwice, Poland
pp. 24

Chip Assemblers: Concepts and Capabilities (PDF)

R.H. Katz , Computer Sciences Department, University of Wisconsin-Madison, Madison, WI
pp. 25-30

A Vertically Integrated VLSI Design Environment (PDF)

J. Rosenberg , Microelectronics Center of North Carolina, Research Triangle Park, NC
pp. 31-38

IBM FSD VLSI Chip Design Methodology (PDF)

K. Ahdoot , IBM Corporation, Federal Systems Division, Manassas, VA
pp. 39-45

The IC Module Compiler, A VLSI System Design Aid (PDF)

N.J. Elias , Bell Laboratories, Holmdel, NJ
pp. 46-49

On Fault Detection in CMOS Logic Networks (PDF)

Kuang-Wei Chiang , Department of Electrical Engineering University of Ottawa
pp. 50-56

A New Integrated System for PLA Testing and Verification (PDF)

F. Somenzi , SGS ATES Componenti Elettronici Central R & D, Agrate Brianza, Italy
pp. 57-63

Test Generation for MOS Circuits Using D-Algorithm (PDF)

S.K. Jain , Bell Laboratories, Murray Hill, NJ
pp. 64-70

Engineering Workstations: Tools or Toys? (PDF)

S. Sapiro , CAE SYSTEMS, INC., Sunnyvale, CA
pp. 79-80

Design/synthesis workshop session (PDF)

J.R. Logan , Hughes Aircraft Company Ground Systems Group, Fullerton, CA
pp. 81-82

An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints (PDF)

Y.Z. Liao , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 107-112

Graph-Optimization Techniques for IC Layout and Compaction (PDF)

G. Kedem , Computer Science Department, University of Rochester, Rochester, NY
pp. 113-120

Improved Compaction by Minimized Length of Wires (PDF)

W.L. Schiele , Lehrstuhl fur Netzwerktheorie und Schaltungstechnik, Technische Universitat Munchen, Munchen, W. Germany
pp. 121-127

Tutorial - Group technology (PDF)

H.R. Prasad , Ford Motor Company
pp. 128

Computer Aided Software Engineering (CASE) (PDF)

F.W. Day , Bell Laboratories, Holmdel, NJ
pp. 129-136

Software Architecture for the Implementation of a Computer-Aided Engineering System (PDF)

C.L. Leath , Hewlett Packard Engineering Productivity Division, Cupertino, CA
pp. 137-142

Placement Algorithms for Custom VLSI (PDF)

K.J. Supowit , Hewlett-Packard Laboratories, Palo Alto, CA
pp. 164-170

A Module Interchange Placement Machine (PDF)

A. Iosupovici , San Diego State University Dept. of Electrical & Computer Engineering, San Diego, CA
pp. 171-174

Incorporating the Human Factor in Color CAD Systems (PDF)

F.S. Frome , Bell Laboratories, Holmdel, NJ
pp. 189-195

Diagnosis of TCM Failures in the IBM 3081 Processor Complex (PDF)

N.N. Tendolkar , International Business Machines Corporation, Poughkeepsie, NY
pp. 196-200

Quality Level and Fault Coverage for Multichip Modules (PDF)

K.E. Torku , IBM General Technology Division, East Fishkill, Hopewell Junction, NY
pp. 201-206

Functional Testing of Digital Systems (PDF)

Kwok-Woon Lai , Bell Laboratories, Murray Hill, NJ
pp. 207-213

Formal Verification of a Real-Time Hardware Design (PDF)

Z.D. Umrigar , Department of Electrical Engineering, Syracuse University, Syracuse, NY
pp. 221-227

Formal Design Verification of Digital Systems (PDF)

A.S. Wojcik , Department of Computer Science, Illinois Institute of Technology, Chicago, IL
pp. 228-234

Automating mask layout and specification - Panel session (PDF)

R.B. Cutler , Bell Laboratories, Allentown, PA
pp. 235-236

An Overview of the Design and Verification Subsystem of the Engineering Design System (PDF)

L.N. Dunn , International Business Machines Corporation, Poughkeepsie, NY
pp. 237-238

Structured Design Verification: Function and Timing (PDF)

C.J. Rimkus , International Business Machines Corporation, Poughkeepsie, NY
pp. 246-252

Design Through Transformation (PDF)

J.B. Bendas , International Business Machines Corporation, Poughkeepsie, NY
pp. 253-256

Routing Method for VLSI Design Using Irregular Cells (PDF)

H.-J. Rothermel , Universitat Karlsruhe, W. Germany
pp. 257-262

Reducing Channel Density in Standard Cell Layout (PDF)

K.J. Supowit , Hewlett-Packard Laboratories, Palo Alto, CA
pp. 263-269

Pictures with Parentheses: Combining Graphics and Procedures in a VLSI Layout Tool (PDF)

R.N. Mayo , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 270-276

Importance of Device Independence to the CADCAM Industry (PDF)

J.R. Warner , Precision Visuals, Inc., Boulder, CO
pp. 277-278

A Multiple Media Delay Simulator for MOS LSI Circuits (PDF)

K. Okazaki , LSI Research and Development Laboratory, Mitsubishi Electric Corporation, Hyogo, Japan
pp. 279-285

Design Aids for the Simulation of Bipolar Gate Arrays (PDF)

P. Kozak , Bell Laboratories, Murray Hill, NJ
pp. 286-292

An Improved Switch-Level Simulator for MOS Circuits (PDF)

V. Ramachandran , Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ
pp. 293-299

Design for Test Calculus: An Algorithm for DFT Rules Checking (PDF)

D.K. Bhavsar , General Electric Company Electronics Laboratory, Syracuse, NY
pp. 300-307

Measured Performance of a Programmed Implementation of the Subscripted D-Algorithm (PDF)

C. Benmehrez , Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY
pp. 308-315

Classes of Diagnostic Tests (PDF)

C. Paulson , Department of Computer Science, Stanford University, Stanford, CA
pp. 316-322

Petri Net Based Search Directing Heuristics for Test Generation (PDF)

K.E. Torku , IBM, General Technology Division, East Fishkill, Hopewell Junction, NY
pp. 323-330

HEX: An Instruction-Driven Approach to Feature Extraction (PDF)

M. Hofmann , Department of Electrical Engineering and Computer Science, Electronics Research Laboratory, University of California, Berkeley, CA
pp. 331-336

Hierarchical Circuit Extraction with Detailed Parasitic Capacitance (PDF)

G.M. Tarolli , Digital Equipment Corporation, Hudson, MA
pp. 337-345

Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (PDF)

J.D. Bastian , Rockwell International Corporation, Defense Electronics Operations Microelectronics Research & Development, Anaheim, CA
pp. 346-352

A Layout Verification System for Analog Bipolar Integrated Circuits (PDF)

E. Barke , Department of Electrical Engineering, University of Hannover, Germany FR
pp. 353-359

Solid Model in Geometric Modelling System : HICAD (PDF)

S. Tokumasu , Hitachi Research laboratory (Annexe), Hitachi Ltd., Ibaraki, Japan
pp. 360-366

Integration of Solid Modeling and Data Base Management for CAD/CAM (PDF)

Y.C. Lee , School of Electrical Engineering, Purdue University, West Lafayette, IN
pp. 367-373

UNIGRAFIX (PDF)

C.H. Sequin , Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
pp. 374-381

VERDI: A Computer Aided Design System for Development and City Planning (PDF)

M. Bouyat , Laboratoire Methodes - Departement G.C.U., INSA de Lyon, Departement Informatique, C.E.R.T. Toulouse
pp. 382-385

Workshop - Technology Design Rules for Design Automation (PDF)

R. Waxman , IBM Federal Systems Division, Manassas, VA
pp. 387-388

Technology Rules - The Other Side of Technology Dependent Code (PDF)

M.F. Heilweil , IBM General Technology Division, East Fishkill Facility, Hopewell Junction, NY
pp. 389

Technology-Independent Circuit Layout (PDF)

R.J. Smith , VR Information Systems, Austin, TX
pp. 390-393

Technology Design Rules - A User's Perspective (PDF)

T.R. Reinke , Honeywell - Solid State Electronics Division, Plymouth, MN
pp. 394

Position Paper Role of Technology Design Rules in Design Automation (PDF)

G.J. Von Ehr , Texas Instruments Incorporated, Dallas, TX
pp. 395

Statistical Techniques of Timing Verification (PDF)

J.H. Shelly , IBM Data Systems Division, Poughkeepsie, NY
pp. 396-402

Path Delay Analysis for Hierarchical Building Block Layout System (PDF)

E. Tamura , IC Design Dept., Semiconductor Gp. SONY Corporation, Atsugishi, Japan
pp. 403-410

Timing Analysis for nMOS VLSI (PDF)

N.P. Jouppi , Department of Electrical Engineering, Stanford University
pp. 411-418

The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance (PDF)

J.J. Granacki , University of Southern California, Los Angeles, CA
pp. 419-424

APSS: An Automatic PLA Synthesis System (PDF)

M.W. Stebnisky , RCA Advanced Technology Laboratories, Camden, NJ
pp. 430-435

Integrated Computer Aided Design, Documentation and Manufacturing System for PCB Electronics (PDF)

M. Tervonen , Technical Research Centre of Finland Electronics Laboratory, OULU, FINLAND
pp. 436-443

Minimizing PWB NC Drilling (PDF)

J.D. Litke , Photocircuits Division of Kollmorgen
pp. 444-447

Partitioning and Placement Technique for Bus-Structured PWB (PDF)

G. Odawara , Department of Precision Engineering, Faculty of Engineering University of Tokyo, Tokyo, Japan
pp. 449-456

Linear Ordering and Application to Placement (PDF)

Sungho Kang , Computer Research Center, Hewlett-Packard Laboratories, Palo Alto, CA
pp. 457-464

Placement of Circuit Modules Using a Graph Space Approach (PDF)

K. Fukunaga , Electrical and Computer Engineering Department, University of Massachusetts, Amherst, MA and Department of Electrical Engineering, University of Osaka Prefecture, Osaka, Japan
pp. 465-471

Computer-Aided Partitioning of Behavioral Hardware Descriptions (PDF)

M.C. McFarland , Dept. of Computer Science, Boston College, Chestnut Hill, MA and Bell Laboratories, Murray Hill, NJ
pp. 472-478

The VLSI Design Automation Assistant: Prototype System (PDF)

T.J. Kowalski , Electrical Engineering Department Carnegie-Mellon University and Bell Laboratories, Murray Hill, NJ
pp. 479-483

A Method of Automatic Data Path Synthesis (PDF)

C.Y. Hitchcock , Electrical Engineering Department, Carnegie-Mellon University
pp. 484-489

Facet: A Procedure for the Automated Synthesis of Digital Systems (PDF)

Chia-Jeng Tseng , Departments of Electrical Engineering and Computer Science, Carnegie-Mellon University, Pittsburgh, PA
pp. 490-496

N.mPc: A Retrospective (PDF)

C.W. Rose , Department of Computer Engineering and Science, Case Institute of Technology, Case Western Reserve University, Cleveland, OH
pp. 497-505

Functional Models for VLSI Design (PDF)

R.L. Druian , Motorola Inc. Microprocessor Design, Austin, TX
pp. 506-514

The N.2 System (PDF)

G.M. Ordy , Dept. of Computer Engineering and Science, Case Western Reserve University, Cleveland, OH
pp. 520-526

Computer Aided Programming (PDF)

P. Bassett , NETRON INC., Toronto, Canada
pp. 527-529

Bounds on the Saved Area Ratio Due to PLA Folding (PDF)

Wentai Liu , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC
pp. 538-544

PRONTO: Quick PLA Product Reduction (PDF)

J.F. Martinez-Carballido , Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR
pp. 545-552

Optimum Reduction of Programmable Logic Array (PDF)

T.C. Hu , Department of Electrical Engineering and Computer Sciences, University of California, San Diego, La Jolla, CA
pp. 553-558

Panel Discussion - Robots in Design (PDF)

E.L. Hall , Department of Electrical Engineering, University of Tennessee, Knoxville, TN
pp. 559

Heuristics for the Circuit Realization Problem (PDF)

J. Cohoon , University of Minnesota
pp. 560-566

Some Computer Aided Engineering System Design Principles (PDF)

H.L. Nattrass , Engineering Productivity Division, Hewlett-Packard Company, Cupertino, CA
pp. 571-577

General River Routing Algorithm (PDF)

Chi-Ping Hsu , Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA
pp. 578-583

A New Channel Routing Problem (PDF)

H.W. Leong , Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 584-590

Hierarchical Channel Router (PDF)

M. Burstein , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 591-597

The Relational Data Model for Design Automation (PDF)

M.N. Haynie , Amdahl Corp., Sunnyvale, CA
pp. 599-607

Edisim and Edicap: Graphical Simulator Interfaces (PDF)

D.D. Hill , Bell Laboratories, Murray Hill, NJ
pp. 608-614

An Algebra for Logic Strength Simulation (PDF)

P.L. Flake , Cirrus Computers Ltd. Howell Building, Uxbridge, Middx. U. K.
pp. 615-618

A Data Structure for MOS Circuits (PDF)

Chi-Yuan Lo , Bell Laboratories, Murray Hill, NJ
pp. 619-624

VHSIC Hardware Description (VHDL) Development Program (PDF)

A. Dewey , Air Force Wright Aeronautical Laboratories AFWAL/AADE, Wright-Patterson Air Force Base, OH
pp. 625-628

Automatic Routing of Double Layer Gate Arrays Using a Moving Cursor (PDF)

B.D. Prazic , GEC Research Laboratories, Hirst Research Centre, Wembley, UK
pp. 644-650

Optimisation of Global Routing for the UK5000 Gate Array by Iteration (PDF)

C.O. Newton , Ministry of Defence (PE) Royal Signals and Radar Establishment, Malvern, Worcestershire, UK
pp. 651-657

Automatic Layout for Gate Arrays with One Layer of Metal (PDF)

P. Robinson , Cambridge University Computer Laboratory, Cambridge, England
pp. 658-664

An Over-Cell Gate Array Channel Router (PDF)

H.E. Krohn , Advanced Technology, Control Data Corporation, Arden Hills, MN
pp. 665-670

A New Statistical Model for Gate Array Routing (PDF)

A.E. Gamal , Information Systems Lab., Stanford University, Stanford, CA.
pp. 671-674

A Topology for Semicustom Array-Structured LSI Devices, and Their Automatic Customisation (PDF)

P. Jennings , School of Electrical Engineering, University of Bath, Bath, Avon, UK
pp. 675-681

Automatic Batch Processing in Multilayer Ceramic Metallization (PDF)

N. DalCero , IBM Corporation, General Technology Division, East Fishkill, Hopewell Junction, NY
pp. 682-685

Test Strategy for Microprocessers (PDF)

S.K. Jain , Dept. of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA
pp. 703-708

Total Stuck-at-Fault Testing by Circuit Transformation (PDF)

A.S. LaPaugh , Department of Electrical Engineering and Computer Science, Princeton University
pp. 713-716

Testing for Bridging Faults (Shorts) in CMOS Circuits (PDF)

J.M. Acken , Sandia National Laboratories, Albuquerque, NM
pp. 717-718

ILS -- Interactive Logic Simulator (PDF)

G.D. Jordan , HP Design Aids, Hewlett-Packard Co., Cupertino, CA
pp. 719-720

ACE: A Circuit Extractor (PDF)

A. Gupta , Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA
pp. 721-725

MACH: A High - Hitting Pattern Checker for VLSI Mask Data (PDF)

A. Tsukizoe , Central Research Laboratory, Hitachi Ltd., Tokyo, JAPAN
pp. 726-731

Consistency Checking for MOS/VLSI Circuits (PDF)

Ning-San Chang , HP Design Aids, Hewlett-Packard Co, Cupertino, CA
pp. 732-733

Space Efficient Algorithms for VLSI Artwork Analysis (PDF)

T.G. Szymanski , Bell Laboratories, Murray Hill, NJ
pp. 734-739

Experiments with the SLIM Circuit Compactor (PDF)

R.C. McGarity , Motorola, Inc., MOS Integrated Circuit Group, Microcomponent Division, Austin, TX
pp. 740-746

CAF: A Computer-Assisted Floorplanning Tool (PDF)

A. Leblond , Centre National d'Etudes des Telecommunications, Meylan, France
pp. 747-753

Laying the Power and Ground Wires on a VLSI Chip (PDF)

A.S. Moulton , Massachusetts Institute of Technology
pp. 754-755

The Transfer of University Software for Industry Use (PDF)

R. Wyleczuk , Engineering Productivity Division, Hewlett-Packard Company, Cupertino, CA
pp. 756-761

A Graphical Tool for Conceptual Design of Data Base Applications (PDF)

C. Batini , Istituto di Automatica, Universita di Roma, Roma, Italy
pp. 762-773

Behavioral Level Transformation in the CMU-DA System (PDF)

R.A. Walker , Electrical Engineering Department, Carnegie-Mellon University
pp. 788-789

HOPLA - PLA Optinization and Synthesis (PDF)

S. Wimer , NATIONAL SEMICONDUCTOR INC., Hertzeliya, ISRAEL
pp. 790-794

Internal Connection Problem in Large Optimized PLAs (PDF)

S. Chuquillanqui , Computer Architecture Group IMAG, Saint Martin D'Heres, France
pp. 795-802

Microprocessor Systems Modeling with MODLAN (PDF)

A. Pawlak , Institute of Electronics Silesian Technical University, Gliwice, Poland
pp. 804-811
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