The Community for Technology Leaders
19th Design Automation Conference (1982)
Las Vegas, NV, USA
June 14, 1982 to June 16, 1982
ISSN: 0146-7123
ISBN: 0-89791-020-6
TABLE OF CONTENTS

A Survey of the State-of-the-Art of Design Automation - An Invited Presentation (PDF)

M.A. Breuer , University of Southern California, Los Angeles, CA
pp. 1

ROBOTICS: The New Automation Tool (PDF)

H.R. Marcotte , Honeywell Defense Systems Division, New Brighton, Minnesota
pp. 2-8

Design for Testability (PDF)

T.W. Williams , IBM Corporation, Boulder, CO
pp. 9

A Utilitarian Approach to CAD (PDF)

T.J. Thompson , Bell Laboratories, Holmdel, NJ
pp. 23-29

Optimal Single Row Router (PDF)

R. Raghavan , Sperry Univac, Roseville, MN
pp. 38-45

A New Two-Dimensional Routing Algorithm (PDF)

Chi-Ping Hsu , University of California, Berkeley, CA
pp. 46-50

The Yorktown Simulation Engine: Introduction (PDF)

G.F. Pfister , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 51-54

The Yorktown Simulation Engine (PDF)

M.M. Denneau , IBM T. J. Watson Research Center, Yorktown Heights, NJ
pp. 55-59

Software Support for the Yorktown Simulation Engine (PDF)

E. Kronstadt , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 60-64

A Logic Simulation Machine (PDF)

M. Abramovici , Bell Laboratories, Naperville, IL
pp. 65-73

Workshop - Industrial Robotics (PDF)

H.R. Prasad , Ford Motor Company
pp. 74

IBM 3081 System Overview and Technology (PDF)

C.A. Collins , International Business Machines Corporation, Poughkeepsie, NY
pp. 75-82

Design Verification System for Large-Scale LSI Designs (PDF)

M. Monachino , International Business Machines Corporation, Poughkeepsie, NY
pp. 83-90

Operational Aspects of Design Automation for the IBM 3081 (PDF)

R.F. Woodward , International Business Machines Corporation, Poughkeepsie, NY
pp. 91-95

Automated Conversion of Design Data for Building the IBM 3081 (PDF)

V.J. Freund , International Business Machines Corporation, Hopewell Junction, NY
pp. 96-103

A Minimum-Impact Routing Algorithm (PDF)

K.J. Supowit , Hewlett-Packard Laboratories, Palo Alto, CA
pp. 104-112

A Bus Router for IC Layout (PDF)

M. Lie , American Microsystems, Inc., Santa Clara, CA
pp. 129-132

A Depth-First Branch-and-Bound Algorithm for Optimal PLA Folding (PDF)

W. Grass , Fachbereich Informatik, Universitaet Hamburg, Hamburg, W. Germany
pp. 133-140

Optimal Bipartite Folding of PLA (PDF)

J.R. Egan , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 141-146

A Logic Minimizer for VLSI PLA Design (PDF)

B. Teel , Intel Corporation Special Systems Operation, Aloha, OR
pp. 156-162

PHILO - A VLSI Design System (PDF)

R. Donze , IBM Corporation, North Rochester, MN
pp. 163-169

A Linear-Time Heuristic for Improving Network Partitions (PDF)

C.M. Fiduccia , General Electric Research and Development Center, Schenectady, NY
pp. 175-181

The CONLAN Project: Status and Future Plans (PDF)

R. Piloty , Technische Hochschule, Darmstadt, FRG
pp. 202-212

VHSIC HDL (PDF)

J.B. Rawlings , AFWAL Avionics Laboratory, Wright Patterson Air Force Base, OH
pp. 213

Evolution of the Engineering Design System Data Base (PDF)

J.L. Sanborn , IBM General Technology Division, Poughkeepsie, NY
pp. 214-218

Hardware Support for Automatic Routing (PDF)

E. Damm , K. Kaiser & Dr. E. Damm GmbH, Muhlheim, Fed. Rep. Germany
pp. 219-223

Global Wiring on a Wire Routing Machine (PDF)

R. Nair , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 224-231

A Hardware Assisted Design Rule Check Architecture (PDF)

L. Seiler , Massachusetts Institute of Technology, Cambridge, MA
pp. 232-238

Toward CAM-Oriented CAD (PDF)

F. Arbab , University of California, Los Angeles
pp. 239-245

The Planar Package Planner for System Designers (PDF)

W.R. Heller , International Business Machines Corporation, Poughkeepsie, NY
pp. 253-260

Automatic Floorplan Design (PDF)

R.H.J.M. Otten , IBM Thomas J. Watson Research Center, Yorktown Heights and Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 261-267

A Database Management System for Design Engineers (PDF)

J. Bennett , Mentor Graphics Corporation, Portland, OR
pp. 268-273

A Database Approach for Managing VLSI Design Data (PDF)

R.H. Katz , University of Wisconsin-Madison Madison, WI
pp. 274-282

Interactive Symbolic Design for VLSI Modules (PDF)

R.P. Larsen , Rockwell International, Anaheim, CA
pp. 291-299

PAOLA: A Tool for Topological Optimization of Large PLAs (PDF)

S. Chuquillanqui , Computer Architecture Group, IMAG - BP Grenoble, France
pp. 300-306

A Layout Synthesis System for NMOS Gate-Cells (PDF)

J. Luhukay , University of Illinois, Urbana, IL
pp. 307-314

Modular Description/Simulation/Synthesis using DDL (PDF)

S.G. Shiva , University of Ala. in Huntsville, Huntsville, AL
pp. 321-329

The EXCELL Method for Efficient Geometric Access to Data (PDF)

M. Tamminen , Helsinki University of Technology Laboratory of Information Processing Science, Espoo, Finland
pp. 345-351

The Quad-CIF Tree: A Data Structure for Hierarchical On-Line Algorithms (PDF)

G. Kedem , University of Rochester, Rochester, NY
pp. 352-357

Object Data Structures Towards Distributed Graphics Processing (PDF)

D. Grabel , Lexidata Corporation, Billerica, MA
pp. 358-364

SAGA: An Experimental Silicon Assembler (PDF)

A.A. Szepieniec , Sagantec Incorporated, Eindhoven, the Netherlands
pp. 365-370

RIOT -- A Simple Graphical Chip Assembly Tool (PDF)

S. Trimberger , California Institute of Technology, Pasadena, CA
pp. 371-376

Designing Gate Arrays Using a Silicon Compiler (PDF)

J.P. Gray , Lattice Logic Ltd, Edinburgh, Scotland
pp. 377-383

Testing Functional Faults in VLSI (PDF)

Yinghua Min , China Academy of Railway Sciences, Beijing, China
pp. 384-392

A Fault Simulation Methodology for VLSI (PDF)

J.P. Hayes , University of Southern California, Los Angeles, CA
pp. 393-399

Design Automation Algorithms: Research and Applications (PDF)

R.J. Lipton , Princeton University, Princeton, NJ
pp. 410

Parametric Pattern Router (PDF)

T. Asano , Osaka Electro-Communication University, Neyagawa, Osaka, Japan
pp. 411-417

A "Greedy" Channel Router (PDF)

R.L. Rivest , MIT Laboratory for Computer Science, Cambridge, MA
pp. 418-424

An Efficient Variable-Cost Maze Router (PDF)

R.K. Korn , Sperry Univac, Blue Bell, PA
pp. 425-431

Automated Rip-Up and Reroute Techniques (PDF)

W.A. Dees , VR Information Systems, Inc., Austin, TX
pp. 432-439

Design of Command for CAD Systems (PDF)

L.A. Price , Calma Company
pp. 453-459

A Symbolic Design System for Integrated Circuits (PDF)

K.H. Keller , University of California, Berkeley, CA
pp. 460-466

The "PI" (Placement And Interconnect) System (PDF)

R.L. Rivest , MIT Laboratory for Computer Science, Cambridge, MA
pp. 475-481

Electronic Chip-In-Place Test (PDF)

P. Goel , Wang Laboratories, Lowell, MA
pp. 482-488

Verification Testing (PDF)

E.J. McCluskey , Stanford University, Stanford, CA
pp. 495-500

Modeling Polyhedral Solids Bounded by Multi-Curved Parametric Surfaces (PDF)

Y.E. Kalay , Carnegie-Mellon University, Pittsburgh, PA
pp. 501-507

A User Interface for Architectural Design, A Case Study (PDF)

G.J. Glass , Carnegie-Mellon University
pp. 508-513

Design of a Graphic Processor for Computer-Aided Drafting (PDF)

C.K. Liu , Carnegie-Mellon University, Pittsburgh, PA
pp. 514-520

An Interactive Drafting System based on two Dimensional Primitives (PDF)

G. Cosmai , Politecnico di Milano, Dipartimento di Meccanica, MILANO
pp. 521-529

Lyra: A New Approach to Geometric Layout Rule Checking (PDF)

M.H. Arnold , University of California, Berkeley, CA
pp. 530-536

DORA: CAD Interface to Automatic Diagnostics (PDF)

R.W. Allen , Western Electric Company, Princeton, NJ
pp. 559-565

Test Generation for Programmable Logic Arrays (PDF)

P. Bose , Coordinated Science Laboratory, Urbana, IL
pp. 574-580

Timing Verification and the Timing Analysis Program (PDF)

R.B. Hitchcock , IBM General Technology Division, Endicott, NY
pp. 594-604

Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips (PDF)

R. Putatunda , RCA Advanced Technology Laboratories, Camden, NJ
pp. 616-621

Synchronous Path Analysis in MOS Circuit Simulator (PDF)

V.D. Agrawal , Bell Laboratories, Murray Hill, NJ
pp. 629-635

Simplified Data Structure for "Mini-Based" Turnkey CAD Systems (PDF)

J. Peled , Gerber Systems Technology, Inc., Windsor, CT
pp. 636-642

Making the Wire Frame Solid (PDF)

D. Robbins , Sandia National Laboratories, Albuquerque, NM
pp. 650-654

On finding Most Optimal Rectangular Package Plans (PDF)

K. Maling , International Business Machines Corporation, Poughkeepsie, NY
pp. 663-670

A Combined Force and Cut Algorithm for Hierarchical VLSI Layout (PDF)

G.J. Wipfler , Institut fur theoretische Elektrotechnik, Universitat Karlsruhe, Germany
pp. 671-677

Transmission Gate Modeling in an Existing Three-Value Simulator (PDF)

R.M. McDermott , ITT LSI Technology Center, Shelton, CT
pp. 678-681

A Design System Approach to Data Integrity (PDF)

W.A. Noon , International Business Machines Corporation, Kingston, NY
pp. 699-705

QCADS--A LSI CAD System for Minicomputer (PDF)

Xian-long Hong , Tsinghua University, Beijing, People's Republic of China
pp. 706-711

Logic Simulation for LSI (PDF)

K. Hirakawa , OKI Electric Industry Co., Ltd., Tokyo, Japan
pp. 755-761

VLSI Design Methodology Workshop (PDF)

J.D. Nash , Raytheon Company, Bedford, MA
pp. 762

Digital Logic Modeling System based on MODLAN (PDF)

A. Pawlak , Institute of Electronics Silesian Technical University, Gliwice, POLAND
pp. 763-770

VEEP - A Vector Editor and Preparer (PDF)

S.J. Gelman , Western Electric Engineering Research Center, Princeton, NJ
pp. 771-776

Hierarchical Top-Down Layout Design Method for VLSI Chip (PDF)

T. Adachi , Musashino Electrical Communication Lab., Nippon Tel. Tel. Public Corp., Musashino, Japan
pp. 785-791

A formal method for computer design verification (PDF)

V. Pitchumani , Syracuse University, Syracuse, NY
pp. 809-814

Formal Semantics for the Automated Derivation of Micro-Code (PDF)

R.A. Mueller , Colorado State University, Fort Collins, CO
pp. 815-824

Logical Correctness by Construction (PDF)

S.M. Leinwand , University of Illinois, Chicago
pp. 825-831

A Verification Technique for Hardware Designs (PDF)

F. Maruyama , Software Laboratory FUJITSU Laboratories Ltd., Kawasaki, Japan
pp. 832-841

Computer System Design Description (PDF)

Yaohan Chu , University of Maryland, College Park, MD
pp. 842-850

Top Down Design and Testability of VLSI Circuits (PDF)

Ph. Basset , Laboratory IMAG, GRENOBLE, FRANCE
pp. 851-857

An Interactive Logic Synthesis System Based upon AI Techniques (PDF)

N. Kawato , Software Laboratory, FUJITSU Laboratories Ltd., Kawasaki, Japan
pp. 858-864

A Language for a Scientific and Engineering Database System (PDF)

T.M. Sparr , University of Texas at Arlington, Arlington, TX
pp. 865-871

A Design Methodology based upon Symbolic Layout and Integrated CAD Tools (PDF)

A.M. Beyls , Centre National d'Etudes des Telecommunications, CNS, MEYLAN, FRANCE
pp. 872-878

Optimum Placement of Two Rectangular Blocks (PDF)

M.S. Chandrasekhar , University of Southern California, Los Angeles, CA
pp. 879-886

On Routing for Custom Integrated Circuits (PDF)

Z. Syed , Stanford University, Stanford, CA
pp. 887-893

On Routing Two-Point Nets Across a Channel (PDF)

R.Y. Pinter , Massachusetts Institute of Technology, Cambridge, MA
pp. 894-902

Measurements of a VLSI Design (PDF)

J.K. Ousterhout , University of California Berkeley, CA
pp. 903-908

Distributed Computation for Design Aids (Abstract)

S.Y. Levy , Rutgers, the State University of New Jersey, New Brunswick, New Jersey
pp. 909-916
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