The Community for Technology Leaders
Design Automation Conference (1981)
Nashville, TN, USA USA
June 29, 1981 to July 1, 1981
TABLE OF CONTENTS

DAC'81 [Cover] (PDF)

pp. c1

CAD for Military Systems, An Essential Link to LSI, VLSI and VHSIC Technology (PDF)

R. Reitmeyer , US Army Electronics Technology & Devices Laboratory, Electronics Research & Development Command (ERADCOM), Fort Monmouth, NJ
pp. 3-12

Recent Developments in Representation in the Science of Design (PDF)

C.M. Eastman , Carnegie-Mellon University, Pittsburgh, PA
pp. 13-21

An Algorithm for Searching Shortest Path by Propagating Wave Fronts in Four Quadrants (PDF)

Xiong Ji-Guang , Shanghai Institute of Metallurgy Academy of Sciences of China, SHANGHAI, CHINA
pp. 29-36

Computation of Power Supply Nets in VLSI Layout (PDF)

H.-J. Rothermel , Institut fur theoretische Elektrotechnik Universitat Karlsruhe, Germany
pp. 37-42

Design Automation Status in Japan (PDF)

A. Yamada , Nippon Electric Co., Ltd., Tokyo, Japan
pp. 43-50

Creating and Updating Space Occupancy and Building Plans using Interactive Graphics (PDF)

R.A. Scoble , Bell Telephone Laboratories, Inc., Whippany, NJ
pp. 66-73

Interactive Shape Generation and Spatial Conflict Testing (PDF)

Y.E. Kalay , Carnegie-Mellon University, Pittsburgh, PA
pp. 75-81

Deterministic Systems Design from Functional Specifications (PDF)

H. Wojtkowiak , Universitat Karlsruhe, Karlsruhe, West Germany
pp. 98-104

Hierarchical Design Verification for Large Digital Systems (PDF)

T. Sasaki , Nippon Electric Co., Ltd., Fuchu City, Tokyo, JAPAN
pp. 105-112

A Critical Path Delay Check System (PDF)

R. Kamikawai , Central Research Laboratory, Hitachi Ltd., Tokyo, Japan
pp. 118-123

Survey of Analysis, Simulation and Modeling for Large Scale Logic Circuits (PDF)

A.E. Ruehli , IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 124-129

Routing of Printed Circuit Boards (PDF)

S. Aranoff , A. D. A., Ministry of Defense, Haifa, Israel
pp. 130-136

On the Use of the Linear Assignment Algorithm in Module Placement (PDF)

S.B. Akers , General Electric Company, Syracuse, NY
pp. 137-144

Mechanical Design Automation in IBM Poughkeepsie (PDF)

G.W. Curl , International Business Machines Corporation, Poughkeepsie, NY
pp. 166-170

Application of Volumetric Modeling to Mechanical Design and Analysis (PDF)

D.L. Dewhirst , MDSI, A Schlumberger Company, Ann Arbor, MI
pp. 171-178

A Perspective View of the MODCON System (PDF)

Y.K. Chan , The Chinese University of Hong Kong, Hong Kong
pp. 179-188

A Maximal Resolution Guided-Probe Testing Algorithm (PDF)

M. Abramovici , Bell Telephone Laboratories, Naperville, IL
pp. 189-195

LSI Product Quality and Fault Coverage (PDF)

V.B. Agrawal , Bell Laboratories, Murray Hill, NJ
pp. 196-203

An Algorithmic Pretest Development for Fault Identification in Analog Networks (PDF)

V. Masurka , Digital Equipment Corporation, Maynard, MA
pp. 204-212

Hardware Description Levels and Test for Complex Circuits (Abstract)

C. Bellon , Laboratoire IMAG BP., GRENOBLE, FRANCE
pp. 213-219

Automatic Generation and Characterization of CMOS Polycells (PDF)

C.M. Lee , Bell Telephone Laboratories, Inc., Murray Hill, NJ
pp. 220-224

Virtual Grid Symbolic Layout (PDF)

N. Weste , Bell Laboratories, Holmdel, NJ
pp. 225-233

Combining Graphics and a Layout Language in a Single Interactive System (PDF)

S. Trimberger , California Institute of Technology, Pasadena, CA and XEROX Palo Alto Research Center, Palo Alto, CA
pp. 234-239

The Cell Design System (PDF)

D. Franco , Xerox Electronics Division, El Segundo, CA
pp. 240-247

Diagnostic System for Large Scale Logic Cards and LSI'S (PDF)

S. Goshima , Hitachi Research Laboratory Hitachi, Ltd., Ibaragi, Japan
pp. 256-259

PODEM-X: An Automatic Test Generation System for VLSI Logic Structures (PDF)

P. Goel , nternational Business Machines Corporation, Poughkeepsie, NY
pp. 260-268

Digital System Simulation: Current Status and Future Trends or Darwin's Theory of Simulation (PDF)

M.A. Breuer , Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
pp. 269-275

Bolt - A Block Oriented Design Specification Language (PDF)

D. Holt , American Microsystems, Inc., Santa Clara, CA
pp. 276-279

A MOS/LSI Oriented Logic Simulator (PDF)

D. Holt , American Microsystems Inc., Santa Clara, CA
pp. 280-287

A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters (PDF)

P. Ng , American Microsystems, Inc., Santa Clara, CA
pp. 288-292

A State-Machine Synthesizer -- SMS (PDF)

D.W. Brown , Tektronix, Inc., Beaverton, OR
pp. 301-305

Automatic Generation of Cells for Recurrence Structures (PDF)

A. Bilgory , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 306-313

Overview of an Arithmetic Design System (PDF)

D.E. Atkins , The University of Michigan, Ann Arbor, MI
pp. 314-321

Position Statement - Tools for Design Automation from a University Point of View (PDF)

R.N. Dutton , Integrated Circuits Laboratory, Stanford University, Stanford, CA
pp. 333

Position Paper Changing the Government's Role in Design Automation (PDF)

J.M. Gould , National Aeronautics And Space Administration, Marshall Space Flight Center, Al
pp. 334-335

Government Interest and Involvement in DA from the Sandia Viewpoint (PDF)

C.W. Gwyn , Sandia National Laboratories, Albuquerque, NM
pp. 336

Current Issues in Government Interest and Involvement in CAD (PDF)

P. Losleben , Department of Defense, Fort George G. Meade, MD
pp. 337-341

Government Actions to Increase CAD Software Productivity (PDF)

D. Nash , Raytheon Company, Bedford, MA
pp. 342

Position Paper Design Automation - A Perspective (PDF)

H.W. Spence , Texas Instruments, Inc., Dallas, TX
pp. 343

Government Interest and Involvement in Design Automation Development The VHSIC Perspective (PDF)

L.W. Sumney , Office of the Under Secretary of Defense Research and Engineering
pp. 344-346

Automatic Test Generation for Stuck-Open Faults in CMOS VLSI (PDF)

Y.M. Elzig , Honeywell, Inc., Bloomington, Minnesota
pp. 347-354

Random Fault Analysis (PDF)

R.M. McDermott , ITT-LSI Systems Support Center, Milford, Connecticut
pp. 360-364

Verification and Optimization for LSI & PCB Layout (PDF)

H.N. Brady , V-R Information Systems, Inc., Austin, TX
pp. 365-371

Performance of Interconnection Rip-Up and Reroute Strategies (PDF)

W.A. Dees , V-R Information Systems, Inc., Austin, TX
pp. 382-390

Automatic PLA Synthesis from a DDL-P Description (PDF)

S. Kang , Stanford University, Stanford, CA
pp. 391-397

Optimization of the PLA Area (PDF)

J.F. Paillotin , Laboratoire IMAG, GRENOBLE, FRANCE
pp. 406-410

Partitioning for VLSI Placement Problems (PDF)

A.M. Patel , Sperry Univac, Blue Bell, PA
pp. 411-418

Placement of Variable Size Circuits on LSI Masterslices (PDF)

K.H. Khokhani , International Business Machines, Inc., East Fishkill Hopewell Junction, NY
pp. 426-434

A CAD System for Logic Design Based on Frames and Demons (PDF)

T. Saito , FUJITSU Laboratories Ltd., Kawasaki, Japan
pp. 451-456

Defining the Bounding Edges of a SynthaVision Solid Model (PDF)

R. Goldstein , Mathematical Applications Group, Inc., Elmsford, NY
pp. 457-461

Geometric Modeling Technology (PDF)

W. Luts , Sikorsky Aircraft Division of UTC
pp. 462

Interactive Graphics for Volume Modeling (PDF)

R. Wolfe , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 463-470

The Modeling and Synthesis of Bus Systems (PDF)

Chia-Jeng Tseng , Carnegie-Mellon University, Pittsburgh, PA
pp. 471-478

A Technology Relative Logic Synthesis and Module Selection System (PDF)

G.W. Leive , Carnegie-Mellon University, Pittsburgh, PA
pp. 479-485

Process Oriented Logic Simulation (PDF)

S.M. Leinwand , University of Illinois, Chicago, IL
pp. 511-517

GSP: A Logic Simulator for LSI (PDF)

J.R. Armstrong , Virginia Polytechnic Institute and State University, Blacksburg, VA
pp. 518-524

Vector Coding Techniques for High Speed Digital Simulation (PDF)

H.E. Krohn , Control Data Corporation, Arden Hills, Minnesota
pp. 525-529

Computer-Aided Computer-Aided Design: Improving CAD Programmer Productivity (PDF)

S. Wong , Hughes Aircraft Company, Culver City, CA
pp. 540-545

INCOD: A System for Interactive Conceptual Data Base Design (PDF)

C. Batini , Istituto di Automatica - Facolta di Ingegneria, Roma,Italy
pp. 546-554

An O (N log N) Algorithm for Boolean Mask Operations (PDF)

U. Lauther , SIEMENS AG, Munich, FRG
pp. 555-562

A Concurrent Pattern Operation Algorithm for VLSI Mask Data (PDF)

T. Kozawa , Central Research Laboratory, Hitachi Ltd., Tokyo, Japan
pp. 563-570

Efficient Boolean Operations on IC Masks (PDF)

J.A. Wilmore , University of California, Berkeley, CA
pp. 571-579

Domain Knowledge and the Design Process (PDF)

J. McDermott , Carnegie-Mellon University, Pittsburgh, PA
pp. 580-588

A CODASYL CAD Data Base System (PDF)

G. Zintl , SIEMENS AG Central Division of Technology, Munchen, Germany
pp. 589-594

A Vertically Organized Computer-Aided Design Data Base (PDF)

K.A. Roberts , GTE Laboratories Incorporated, Waltham, MA
pp. 595-602

The Analog Behavior of Digital Integrated Circuits (PDF)

L.A. Glasser , Massachusetts Institute of Technology, Cambridge, MA
pp. 603-612

Signal Delay in RC Tree Networks (PDF)

P. Penfield , Massachusetts Institute of Technology, Cambridge, MA
pp. 613-617

User Documentation for Design Automation at TI (PDF)

D.M. Sims , Texas Instruments Incorporated, Dallas, TX
pp. 623-631

PRIMEAIDS: An Integrated Electrical Design Environment (PDF)

R. Cleghorn , PR1ME Computer, Inc., Framingham, MA
pp. 632-638

Data Structures for CAD Object Description (PDF)

M. Lacroix , Philips Research Laboratory, Brussels, Belgium
pp. 653-659

Some Properties of a Probabilistic Model for Global Wiring (PDF)

D. Wallace , IBM General Technology Division, East Fishkill Hopewell Junction, NY
pp. 660-667

Aiming at a General Routing Strategy (PDF)

J. Heinisch , C.I.I. Honeywell Bull, Les Clayes sous Bois, France
pp. 668-675

Contrasts in Physical Design between LSI and VLSI (PDF)

W.R. Heller , International Business Machines Corporation, Poughkeepsie, NY
pp. 676-683

Circuit Recognition and Verification Based on Layout Information (PDF)

I. Ablasser , AEG-Telefunken, Semiconductor Department, Heilbronn, F.R. Germany
pp. 684-689

PANAMAP-B: A Mask Verification System for Bipolar IC (PDF)

J. Yoshida , Wireless Research Labolatory, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
pp. 690-695

Custom VLSI Electrical Rule Checking in an Intelligent Terminal (PDF)

L.V. Corbin , Boeing Aerospace Company, Seattle, WA
pp. 696-701

The "Gap" Between Users and Designers of CAD/CAM Systems: Search for Solutions (PDF)

J. Peled , Gerber Systems Technology, Inc., South Windsor, CT
pp. 703-705

The Role of Engineering in the Evolving Technology/Automation Interface (PDF)

P.E. Barck , Digital Equipment Corporation, Tewksbury, MA
pp. 706-707

What to do When the Seat of Your Pants Wears Out--The Formalization of the VLSI Design Process (PDF)

E. Burdick , Digital Equipment Corporation--Semiconductor Engineering Group
pp. 708-709

Position Paper the Effects of CAD on the Engineering Organization (PDF)

P. Felton , Raytheon Electromagnetic Systems Division, Goleta, CA
pp. 710-711

Total Verification of Printed Circuit Artwork (PDF)

M.A. Ward , Sperry Univac General Systems Division, Salt Lake City, Utah
pp. 720-725

Automatic VLSI Layout Verification (PDF)

L. Williams , Xerox Corporation, El Segundo, CA
pp. 726-732

An Optimum Layer Assignment for Routing in ICs and PCBs (PDF)

M.J. Ciesielski , University of Rochester, Rochester, NY
pp. 733-737

TWIGY A Topological Algorithm Based Routing System (PDF)

M.T. Doreau , Digital Equipment Corporation, Maynard, MA
pp. 746-755

A Preprocessor for Channel Routing (PDF)

M.H. Young , CAD Department STC-Microtech Corp., Sunnyvale, CA
pp. 756-761

A Dogleg "Optimal" Channel Router with Completion Enhancements (PDF)

M.M. Wada , Sandia National Laboratories, Albuquerque, NM
pp. 762-768

A Statistical Model for Net Length Estimation (PDF)

Lai-Chering Suen , Bell Laboratories, Naperville, IL
pp. 769-774

MOSSIM: A Switch-Level Simulator for MOS LSI (PDF)

R.E. Bryant , Massachusetts Institute of Technology, Cambridge, MA
pp. 786-790

Functional Modelling for Logic Simulation (PDF)

P.G. Raeth , Air Force Institute of Technology Wright-Patterson Air Force Base, Dayton, OH
pp. 791-795

AIDE - A Tool for Computer Architecture Design (PDF)

D.J. Ellenberger , Bell Telephone Laboratories, Naperville, IL
pp. 796-803

MILD - A Cell-Based Layout System for MOS-LSI (PDF)

K. Sato , LSI R&D Laboratory, Mitsubishi Electric Corporation, Itami, Japan
pp. 828-836

A Parallel Bit Map Processor Architecture for DA Algorithms (PDF)

T. Blank , Stanford University, Stanford, CA and Xerox PARC, Palo Alto, CA
pp. 837-845

On Logic Comparison (PDF)

L. Berman , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 854-861

AREA-Time Efficient Addition in Charge Based Technology (PDF)

R.K. Montoye , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 862-872
91 ms
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