The Community for Technology Leaders
17th Design Automation Conference (1980)
Minneapolis, MN, USA
June 23, 1980 to June 25, 1980
ISBN: 0-89791-020-6
TABLE OF CONTENTS

A Generalized Channel Router (PDF)

D.W. Hightower , Texas Instruments Incorporated
pp. 12-21

A "Grid-free" Channel Router (PDF)

K. Sato , LSI Development Laboratory Mitsubishi Electric Corporation, Hyogo, Japan
pp. 22-31

An Over-The-Cell Router (PDF)

D.N. Deutsch , Bell Laboratories, Murray Hill, NJ
pp. 32-39

Design Automation at a Large Architect-Engineer (PDF)

E.F. Chelotti , Gibbs and Hill, Inc., New York, NY
pp. 40-49

System Facilities for CAD Databases (PDF)

C.M. Eastman , Carnegie-Mellon University, Pittsburgh, PA
pp. 50-56

Weaknesses of Commercial Data Base Management Systems in Engineering Applications (PDF)

T.W. Sidle , Scientific Calculations, Inc., Santa Cruz, CA
pp. 57-61

A New Test Pattern Generation System (PDF)

Y.M. El-ziq , Honeywell, Inc., Bloomington, Minnesota
pp. 62-68

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction (PDF)

M. Abramovici , Bell Telephone Laboratories, Naperville, Illinois
pp. 69-76

Test Generation Costs Analysis and Projections (PDF)

P. Goel , IBM Corporation, Poughkeepsie, NY
pp. 77-84

Issues in IC Implementation of High Level, Abstract Designs (PDF)

J.H. Kim , Carnegie-Mellon University, Pittsburgh, PA
pp. 85-91

Automation of Design for Uncommitted Logic Array (PDF)

F.R. Ramsay , Ferranti Electronics Limited, Microelectronics Centre, Hollinwood, Manchester, England
pp. 100-107

The Standard Transistor Array (STAR) Part I-A Two-Layer Metal Semicustom Design System (PDF)

J.M. Gould , Electronics and Control Laboratory, Marshall Space Flight Center, AL
pp. 108-113

Inter-Active Graphic Methods for Automating Mechanical Engineering Design and Analyses (PDF)

J.M. Miller , Honeywell Electro-Optical Systems Center, Lexington, MA
pp. 114-128

Computer-Aided Assignment of Manufacturing Tolerances (PDF)

A.M. Patel , Sperry Univac, Blue Bell, PA
pp. 129-133

Automation of Sheet Metal Design and Manufacturing (PDF)

D.W. Currier , Motorola, Inc, Schaumburg, IL
pp. 134-138

Verification of Timing Constraints on Large Digital Systems (PDF)

T.M. McWilliams , Lawrence Livermore Laboratory, University of California and Stanford University
pp. 139-147

Development in Verification of Design Correctness (PDF)

W.E. Cory , Stanford University, Stanford, CA
pp. 156-164

A Survey of Space Allocation Algorithms in Use in Architectural Design in the Past Twenty Years (PDF)

R.S. Frew , ARGA Associates, New Haven Southern Connecticut State College and Yale School of Architecture, New Haven, Connecticut
pp. 165-174

Digital Test Generation and Design for Testability (PDF)

J. Grason , Bell Laboratories, Holmdel, NJ
pp. 175-189

SCOAP: Sandia Controllability/Observability Analysis Program (PDF)

L.H. Goldstein , Sandia National Laboratories, Albuquerque, NM
pp. 190-196

The Design and Implementation of Fault Insertion Capabilities for ISPS (PDF)

J.D. Northcutt , Carnegie-Mellon University, Pittsburgh, PA
pp. 197-209

An Accurate Functional Level Concurrent Fault Simulator (PDF)

M.A. d'Abreu , Honeywell Information Systems, Phoenix, AZ
pp. 210-217

An Integrated CAD System for Architecture (PDF)

B.T. David , Laboratoire IMAG, Grenoble Cedex, France
pp. 218-225

A Prestructuring Model for System Arrangement Problems (PDF)

K. Sato , Institute of Design, Illinois Institute of Technology, Chicago, IL
pp. 226-236

A Data Structure for Interactive Placement of Rectangular Objects (PDF)

V. Jayakumar , Louisiana State University, Baton Rouge, LA
pp. 237-242

A Line-Expansion Algorithm for the General Routing Problem with a Guaranteed Solution (PDF)

W. Heyns , Katholieke Universiteit Leuven, Departement Elektrotechniek, Heverlee, Belgium
pp. 243-249

An Implementation of a Saturated Zone Multi-Layer Printed Circuit Board Router (PDF)

M.J. Lorenzetti , V-R Information Systems and University of Texas, Austin, TX
pp. 255-262

An Integrated Mask Artwork Analysis System (PDF)

T. Mitsuhashi , NEC-TOSHIBA Information Systems Inc., Kawasaki,JAPAN
pp. 277-284

SIDS - A Symbolic Interactive Design System (PDF)

D. Clary , American Microsystems, Inc., Santa Clara, CA
pp. 292-295

Interactive Wiring System (PDF)

F.D. Skinner , IBM Data Systems Divison, Hopewell Junction, NY
pp. 296-308

ALEX: A Conversational, Hierarchical Logic Design System (PDF)

K.A. Duke , International Business Machines Corporation, Poughkeepsie, NY
pp. 318-327

Verifying Deep Logic Hierarchies with ALEX (PDF)

G.M. Koppelman , T. J. Watson Research Center, International Business Machines Corporation, Yorktown Heights, NY
pp. 328-335

Design Automation and VLSI in the 80's (PDF)

C.R. McCaw , IBM Data Systems Division, Hopewell Junction, NY
pp. 336-337

Position Statement A Contemporary Perspective on Design Automation and VLSI in the 80's (PDF)

J. Allen , Massachusetts Institute of Technology, Cambridge, MA
pp. 338-339

Position Statement: Design Automation Trends for VLSI in the 1980s (PDF)

C.W. Gwyn , Sandia National Labs., Albuquerque, NM, USA
pp. 340

Position Statement: Design Automation and VLSI in the 80's (PDF)

R.M. Jacobs , Bell Laboratories, Allentown, PA
pp. 341

Position Statement: Design Tools for VLSI (PDF)

B. Lee , CALMA Corporation, Sunnyvale, CA
pp. 342

Position Statement: The VLSI Design Challenge of the 80'S (PDF)

A.R. Newton , University of California, Berkeley, CA
pp. 343-344

Position Statement: VLSI - A Challenge for System Designers (PDF)

M.B. Roberts , Texas Instruments, Inc., Dallas, TXs
pp. 345

Position Statement: Design Automation and VLSI in the 80's (PDF)

S. Sapiro , American Microsystems, Inc., Santa Clara, CA
pp. 346-347

An Interactive Test Data System for LSI Production Testing (PDF)

H.D. Schnurmann , IBM Data Systems Division, Hopewell Junction, NY
pp. 362-366

An Optimized ATPG (PDF)

S. Mourad , Bendix Test Systems Division, Teterboro, NJ
pp. 381-385

Methods for Generalized Deductive Fault Simulation (PDF)

N. Giambiasi , Laboratoire d'Automatique de Montpellier, Universite des Sciences t Techniques du Languedoc, Montpellier-cedex, France
pp. 386-393

The Complexity of Design Automation Problems (PDF)

S. Sahni , University of Minnesota, Minneapolis, MN
pp. 402-411

Complexity Theory and Design Automation (PDF)

W.E. Donath , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 412-419

Design Process Analysis: A Measurement and Analysis Technique (PDF)

K.D. Yates , International Business Machines Corporation, Poughkeepsie, NY
pp. 420-421

The Electronics Engineer's Design Station (PDF)

D.E. Bering , Lawrence Livermore Laboratory, Livermore, CA
pp. 422-429

An Interactive Graphics System for Custom Design (PDF)

P. Carmody , IBM Data Systems Division, Hopewell Junction, NY
pp. 430-439

Technical Documentation by "Magic" (PDF)

J.B. Macdonald , Western Electric Company, Princeton, NJ
pp. 440-445

The Use of Graphics Processors for Circuit Design Simulation at GTE AE Labs (PDF)

J.A. Dyer , GTE Automatic Electric Laboratories, Inc., Northlake, IL
pp. 446-450

Efficient Placement and Routing Techniques for Master Slice LSI (PDF)

H. Shiraishi , FUJITSU LABORATORIES LTD., Kawasaki, JAPAN
pp. 458-464

COMET - A Fast Component Placer (PDF)

V.K. Smith , V-R Information Systems, Austin, TX
pp. 465-471

Algebraic Analysis of Nondeterministic Behavior (PDF)

S. Leinwand , The Weizmann Institute of Science, Rehovot, ISRAEL
pp. 483-493

Automatic Design with Dependence Graphs (PDF)

A.E. Casavant , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 506-515

Position Paper Observations Of A Cad User (PDF)

D.J. Garvin , Cincinnati Milacion, Cincinnati, Ohio
pp. 519

The Interchange Algorithms for Circuit Placement Problems (PDF)

L.C. Cote , State University of New York, College at Geneseo, Geneseo, NY
pp. 528-534

The Genealogical Approach to the Layout Problem (PDF)

A.A. Szepieniec , Eindhoven University of Technology, EINDHOVEN, the Netherlands
pp. 535-542

A New Look at Logic Synthesis (PDF)

J.A. Darringer , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 543-549

Combinational Logic Synthesis from an HDL Description (PDF)

S.G. Shiva , The University of Alabama, Huntsville, AL
pp. 550-555

Practical Automated Design of LSI for Large Computers (PDF)

J.P. Singleton , International Computers Limited Software Technology Development Centre, Manchester, England
pp. 556-559

Table Lookup Techniques for Fast and Flexible Digital Logic Simulation (PDF)

E. Ulrich , Digital Equipment Corporation, Maynard, MA
pp. 560-563

Justification and Financial Analysis for CAD (PDF)

R.E. Powell , E-Systems, ECI Division, St. Petersburg, FL
pp. 564-571

A Prototyping and Simulation Approach to Interactive Computer System Design (PDF)

P.R. Hanau , Martin Marietta Aerospace Denver Division, Denver, CO
pp. 572-578

A Hierarchical Bit-Map Format for the Representation of IC Mask Data (PDF)

J.A. Wilmore , University of California, Berkeley, CA
pp. 585-590

Cell Map Representation for Hierarchical Layout (PDF)

J. Soukup , Bell-Northern Research, Ottawa, Canada
pp. 591-594

SLIM--The Translation of Symbolic Layouts into Mask Data (PDF)

A.E. Dunlop , Bell Laboratories, Murray Hill, NJ
pp. 595-602

A Data Structure for Gridless Routing (PDF)

U. Lauther , Siemens AG, Munich, FRG
pp. 603-609

A Multiple Delay Simulator for MOS LSI Circuits (PDF)

H.N. Nham , Bell Laboratories, Murray Hill, NJ
pp. 610-617

A Mixed-Mode Simulator (PDF)

V.D. Agrawal , Bell Laboratories, Murray Hill, NJ
pp. 618-625

Functional Level Simulation at Raytheon (PDF)

D. Nash , Raytheon Company Missile Systems Division, Bedford, MA
pp. 634-641

Position Statement - CAD for VLSI (PDF)

S.B. Daram , Hughes Aircraft Company, Newport Beach, CA
pp. 642
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