The Community for Technology Leaders
Design Automation Conference (1979)
San Diego, CA, USA USA
June 25, 1979 to June 27, 1979
TABLE OF CONTENTS

A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem (PDF)

S. Goto , Central Research Laboratories, Nippon Electric Co., Ltd., Kawasaki, Japan
pp. 11-17

Incremental Processing Applied to Steinberg's Placement Procedure (PDF)

H.W. Carter , University of Southern California, Los Angeles, CA
pp. 26-31

A Low Cost Satellite for Fast Interactive Graphics in a Time-Sharing Environment (PDF)

B. Meyer , Engineering Division Israel Aircraft Industries Ltd., BenGurion International Airport, Israel
pp. 39-44

Concepts of a Microcomputer Design Language (PDF)

Yaohan Chu , University of Maryland, College Park, Maryland
pp. 45-52

The Mimola Design System a Computer Aided Digital Processor Design Method (PDF)

G. Zimmermann , Institut fur Informatik und Praktische Mathematik Universitat Kiel, Kiel, W-Germany
pp. 53-58

Unified Shapes Checker - A Checking Tool for LSI (PDF)

C.R. McCaw , IBM Data Systems Division, East Fishkill Hopewell Junction, NY
pp. 81-87

LSI Layout Checking Using Bipolar Device Recognition Technique (PDF)

C.S. Chang , IBM Data Systems Division, East Fishkill Hopewell Junction, NY
pp. 95-101

CALMOS : A Portable Software System for the Automatic and Interactive Layout of MOS/LSI (PDF)

H. Beke , Leuven Industrial Software Company, Leuven, Belgium
pp. 102-108

A New Circuit Placement Program for FET Chips (PDF)

K.W. Lallier , IBM General Technology Division, Essex Junction, Vermont
pp. 109-113

An Experimental Input System of Hand-Drawn Logic Circuit Diagram for LSI CAD (PDF)

M. Ishii , Digital Systems Laboratory, FUJITSU LABORATORIES LTD., Kawasaki, JAPAN
pp. 114-120

Stonewalls: Experiments in Intelligent Drafting (PDF)

C.I. Yessios , The Ohio State University, Columbus, Ohio
pp. 128-134

Multiple Fault Diagnosis in Combinational Networks (PDF)

C.W. Cha , IBM Data Systems Division, East Fishkill Hopewell Junction, NY
pp. 149-155

TMEAS, A Testability Measurement Program (PDF)

J. Grason , Bell Laboratories, Holmdel, NJ
pp. 156-161

Behavioral-Level Test Development (PDF)

W.A. Johnson , Texas Instruments Incorporated, Dallas, TX
pp. 171-179

A Procedure for Checking the Topological Consistency of A 2-D or 3-D Finite Element Mesh (PDF)

K. Preiss , Ben-Gurion University of the Negev, Beer Sheva, Israel
pp. 200-296

Macrosimulation with Quasi-General Symbolic FET Macromodel and Functional Latency (PDF)

H.Y. Hsieh , IBM Data Systems Division, East Fishkill Hopewell Junction, NJ
pp. 229-234

Methods of Modelling Digital Devices for Logic Simulation (PDF)

E. Kjelkerud , Royal Institute of Technology, Stockholm, Sweden
pp. 235-241

Digital Logic at the Gate and Functional Level (PDF)

P. Wilcox , Bell-Northern Research, Ottawa, Ontario
pp. 242-248

Efficient Simulation of AHPL (PDF)

Z. Navabi , University of Arizona, Tucson, AZ
pp. 255-262

SILOG: A Practical Tool for Large Digital Network Simulation (PDF)

N. Giambiasi , Laboratoire d'Automatique de Montpellier Universite des Sciences et Techniques du Languedoc, MONTPELLIER, France
pp. 263-271

SABLE: A Tool for Generating Structured, Multi-Level Simulations (PDF)

D. Hill , Computer Systems Lab, Stanford University
pp. 272-279

Symbolic Simulation for Correct Machine Design (PDF)

W.C. Carter , IBM Thomas J. Watson Research Center, Yorktown Heights, NJ
pp. 280-286

Optimal Layout of CMOS Functional Arrays (PDF)

T. Uehara , FUJITSU Laboratories Ltd
pp. 287-289

The Minimum Width Routing of a 2-Row 2-Layer Polycell-Layout (PDF)

T. Kawamoto , Tokyo Institute of Technology, Tokyo, Japan
pp. 290-296

Introduction to Silicon Compilation (PDF)

J.P. Gray , California Institute of Technology, Pasadena, CA
pp. 305-306

IC Specification Language (PDF)

R. Ayres , Xerox Corporation, El Segundo, CA
pp. 307-309

Bristle Blocks: A Silicon Compiler (PDF)

D. Johannsen , California Institute of Technology
pp. 310-313

Silicon Compilation-A Hierarchical Use of PLAs (PDF)

R. Ayres , Xerox Corporation, El Segundo, CA
pp. 314-316

PC Board Layout Techniques (PDF)

D.R. Johnson , Computervision Corporation, Bedford, MA
pp. 337-343

Views of a vendor (PDF)

M.J. Cronin , Computervision Corporation, Bedford, MA
pp. 346

Design Automation Concerns (PDF)

J.B. Kane , IBM Federal Systems Division, Owego, NY
pp. 347-348

Future of Design Automation (PDF)

P. Losleben , Department of Defense, Fort Meade, MD
pp. 349

Moving a da system from development to production (Abstract)

W.G. Magnuson , Lawrence Livermore Laboratory, Livermore, CA
pp. 350-351

Design Automation Philosophies (PDF)

D.L. Peterson , Lear Siegler, Inc., Grand Rapids, Michigan
pp. 353

Design Verification Based on Functional Abstraction (PDF)

S. Leinwand , The Weizmann Institute of Science, Rehovot, Israel
pp. 353-359

Design and Verification of Large-Scale Computers by Using DDL (PDF)

N. Kawato , FUJITSU Laboratories Ltd., Kawasaki, Kanagawa, Japan
pp. 360-366

Logic Verification System for Very Large Computers Using LSI's (PDF)

Y. Ohno , Kanagawa Works, Hitachi, Ltd.,Kanagawa, Japan
pp. 367-374

The Application of Program Verification to Hardware Verification (PDF)

J.A. Darringer , IBM Thomas J. Watson Research Center, Yorktown Heights, N
pp. 375-381

Electron Beam Lithography (PDF)

F.S. Ozdemir , Hughes Research Laboratories, Malibu, CA
pp. 383-391

Hughes S&CG Custom LSI Layouts - 'We Did it Our Way' (PDF)

R.R. Rath , Hughes Aircraft Company
pp. 392-397

A Computer-Aided Design Data Base (PDF)

S. Wong , Hughes Aircraft Company, Culver City, CA
pp. 398-402

Hierarchical Modeling and Simulation in VISTA (PDF)

R.I. Gardner , Hughes Aircraft Company, Canoga Park, CA
pp. 403-405

A Placement Capability Based on Partitioning (PDF)

L.I. Corrigan , Hughes Aircraft Company, Culver City, CA
pp. 406-413

A Design Aids Data Base for Digital Components (PDF)

D.J. Sucher , Washington University, St. Louis, Missouri
pp. 414-420

Descriptive Databases in Some Design/Manufacturing Environments (PDF)

E.M. Hoskins , Applied Research of Cambridge, Cambridge England
pp. 421-436

Component Library for an Integrated DA System (PDF)

K. Nieng , GTE Automatic Electric Laboratories, Northlake, Illinois
pp. 437-444

The Design of an Efficient Data Base to Support an Interactive LSI Layout System (PDF)

J.A. Wilmore , ERL, EECS University of California Berkeley, CA
pp. 445-451

The Complete VLSI Design System (PDF)

M.F. Oakes , Racal-Redac Limited, Tewkesbury, Gloucestershire, England
pp. 452-460

Topological Analysis for VLSI Circuits (PDF)

P. Losleben , Department of Defense, Ft. Meade, MD
pp. 461-473

Placement Algorithms for Arbitrarily Shaped Blocks (PDF)

B.T. Preas , Stanford University, Stanford, CA
pp. 474-480

Global Router (PDF)

J. Soukup , Bell-Northern Research, Ottawa, Canada
pp. 481-484

A "Lookahead" Router for Multilayer Printed Wiring Boards (PDF)

J.C. Foster , Bell Laboratories, Whippany, NJ
pp. 486-493

An Interactive Routing Program with On-Line Clean-Up of Sketched Routes (PDF)

O.A. Larvik , The University of Trondheim, Trondheim, Norway
pp. 500-505

An Introduction to the N. mPc Design Environment (PDF)

F.I. Parke , Case Western Reserve University, Cleveland, Ohio
pp. 513-519

The N. mPc System Description Facility (PDF)

C.W. Rose , Case Western Reserve University, Cleveland, Ohio
pp. 520-528

The N. mPc Runtime Environment (PDF)

F.I. Parke , Case Western Reserve University, Cleveland, Ohio
pp. 529-536

An Evaluation of the N. mPc Design Environment (PDF)

G.M. Ordy , Case Western Reserve University, Cleveland, Ohio
pp. 537-542

Can CAD Meet the VLSI Design Problems of the 80's? (PDF)

D. Gibson , Intel Corporation, Aloha, Oregon
pp. 543

VLSI - A Design Challenge (PDF)

R. Waxman , International Business Machines Corporation, Kingston, NY
pp. 546-547

CAD System for VLSI (PDF)

W. Wiemann , Motorola Inc., Austin, TX
pp. 550

Can CAD Meet the VLSI Design Problems of the 80's? (PDF)

R.P. Larsen , Rockwell International Corporation, Anaheim, CA
pp. 551

Can CAD Meet the VLSI Design Problems of the 80's? (PDF)

D. Hightower , Texas Instruments Incorporated
pp. 552-553

Developments in Computer Simulation of Gate Level Physical Logic - a Tutorial (PDF)

L. Bening , Control Data Corporation, Arden Hills, MN
pp. 561-567
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