The Community for Technology Leaders
Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
ISBN: 978-0-7695-3507-4
pp: 265-269
The H.264 video coding standard has achieved a significant improvement in coding efficiency over previous standards. However, the computational complexity of the H.264 encoder is increased drastically, which results practical difficulties in its implementation on the embedded platform. This paper presents two implementation techniques to optimize the H.264 encoder on the embedded symmetric multiprocessor architecture. We propose a coarse-grained functional partitioning method to balance the load of the encoder among the cores with small overhead of synchronization. On the other hand, we present a memory management optimization method to exploit the memory subsystem on the embedded platform effectively for the H.264 encoder. The experimental results demonstrate that, for the video sequences with VGA format, the performance of the optimized H.264 encoder is greatly improved.
H.264, video coding, symmetric multi-processor, embedded system

Z. Zhou, K. Ouyang and Q. Ouyang, "Optimization and Implementation of H.264 Encoder on Symmetric Multi-processor Platform," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 265-269.
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