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Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
ISBN: 978-0-7695-3507-4
pp: 596-599
A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction-bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.
Cher-Shiung Tsai, Dong-Shong Liang, Jenq-Jong Lu, Cheng-Chi Tai, Yaw-Hwang Chen, Kwang-Jow Gan, Geng-Huang Lan, "Multiple-Valued Memory Design by Standard BiCMOS Technique", Computer Science and Information Engineering, World Congress on, vol. 03, no. , pp. 596-599, 2009, doi:10.1109/CSIE.2009.972
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