Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.44
A method based on the binary decision diagrams (BDD) and Boolean partial derivative for fault test pattern generation is proposed because traditional test pattern generation is difficult to program. This method uses the Shannon expansion to generate BDD from the Boolean expression of logic circuit and develops the XOR operation on BDDs. The single stuck-at fault test pattern generation algorithm is based on BDD and Boolean difference. The double stuck-at faults test BDD is changed into XOR operations on three single stuck-at faults test BDDs, two of which are single stuck-at faults test BDDs and the other is new generated. A recursive algorithm for multiple stuck-at faults test BDD is brought up to do with double stuck-at faults test BDDs. Test vectors are generated from BDD traversal. The results show that this method is effective to generate test vectors of stuck-at faults. It reduces the cost of time and space.
W. Changqian and W. Chenghua, "A Method for Logic Circuit Test Generation Based on Boolean Partial Derivative and BDD," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 499-504.