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Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
ISBN: 978-0-7695-3507-4
pp: 480-483
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectre with 0.13μm CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz Bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 Vpower supply. To the best of the authors’ knowledge, a single stage LNA operating at such high frequency is yet to be reported.
36.1 GHz, Single Stage, Low Noise Amplifier, LNA, Passive Output Matching, 0.13µm CMOS Process

S. S. Rashid, A. Roy, S. N. Ali and A. Rashid, "A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 480-483.
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