Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.166
Traditional CPU instructions provide limited support to the byte permutation operation which is frequently used in the various symmetric encryption algorithms. Due to this reason, researcher Ruby B. Lee at Princeton University presented the byte permutation instructions and proved that the byte permutation instructions played an important role on improving the performance of cryptographic algorithms for general processors. Our attention is emphasized at the hardware implementation of the byte permutation instruction, and we present a byte permutation functional unit which is validated on FPGA of ALTERA’s Cyclone EP1C12Q240C6N. In the end, we present the throughput of the AES algorithm on the hardware implementation. And it is proved that the throughput is nine times higher than the available hardware implementation of AES on a universal architecture.
Cryptographic algorithm, bit permutation operation, functional unit, FPGA validation
Q. Wang and J. Liang, "The Hardware Implementation of Byte Permutation Instruction of an Embedded Processor," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 465-469.