Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.40
In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.
Parallel processing, multi-DSP, real-time processing, hardware architecture
J. Wang, W. Li, W. Zhang and W. Wu, "Design Methods of Multi-DSP Parallel Processing System," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 458-464.