The Community for Technology Leaders
Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
ISBN: 978-0-7695-3507-4
pp: 444-447
It has become clear that on-chip storage is criticalfor most applications on FPGAs. In order to utilize onchip storage efficiently, scholars have done some researches on implementing user memory models with embedded single-port and dual-port arrays. Their work is based on the assumption that user memory models are either single-port or dual-port. However, in some applications, user memory models require 3 or more than 3 ports. Thus, we propose a novel mapping technique in this paper. The principle of this mapping technique is to interleave dual-port arrays to create Nport memory mapping. Data in different arrays can be accessed simultaneously while accessing the same array at the same time will cause conflict. In order to reduce conflict, we use block access mode in our design. Besides, port importance hierarchy is proposed for flexible conflict handling. Experiment results that,compared to the use of distributed rams, our design is a better choice to implement N-port memory.

G. Yijun and W. Zuo, "Mapping N-Port Memory with Dual-Port Array," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 444-447.
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