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Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
ISBN: 978-0-7695-3507-4
pp: 423-427
A low-power 11-transistor Content Addressable Memory (CAM) cell is presented for high performance applications. The CAM cell design is based on the conventional 8-transistor one-read and one-write Register File (RF) cell, where a read operation does not affect the cell stability. In addition, it supports single cycle throughput for write/read and write/CAM operations. Also, read/write operations are independent of the stored and/or search data. Comparison of power and performance under the same condition of noise robustness of dynamic CAM arrays with the proposed CAM cell against three other existing cells as well as a static CAM array is presented. Simulation results based on 32 nm process technology indicate that the proposed cell offers the lowest power and best performance compared to the existing RF based dynamic CAM array designs.
Content Addressable Memory, Low-Power, Domino

A. R. Patwary, B. M. Geuskens and S. L. Lu, "Content Addressable Memory for Low-Power and High-Performance Applications," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 423-427.
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