Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.699
The conventional CMOS pins consume very large energy when driving chip pads because of large load capacitances. This paper reports two adiabatic pad cells for driving the chip pads. The proposed adiabatic pad cells include mainly chip pads, electrostatic discharge (ESD) protection circuits, and two stage adiabatic buffers that are used to drive the large load capacitances on chip pads. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the proposed adiabatic output pad cells are carried out. HSPICE post-simulation shows that the proposed two adiabatic output pad cells attain large energy savings, as compared with the conventional counterpart.
Pad cells, Adiabatic circuits, Low power
B. Liu, X. Luo, J. Hu and D. Zhou, "Low-Power Adiabatic Pins for Driving Chip Pads," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 408-412.