Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.51
This paper presents an all-digital PLL (ADPLL) for the pixel clock regeneration in analog video signal digitization applications. A fine frequency resolution, 1-1-1 MASH structure based fractional-N PLL (FN-PLL) is used as the Digital-Controlled Oscillator (DCO). Two loop filters which are triggered by different clock frequencies and both with adaptive gain controllers are combined together working at different states to increase both the tracking speed and the locked jitter performance. The ADPLL maximum output frequency is determined by the FN-PLL’s voltage-controlled oscillator (VCO) which can be upper than 1Ghz. It covers any VESA and HDTV specification requirements even at 4X over-sampling ratio. A test chip contains this ADPLL prototype has been implemented in a 0.13um CMOS technology. The layout area is about 0.2mm2, the measured RMS jitter is 32.4ps.
Phase locked loop, All-digital PLL, Fractional-N PLL, Low jitter
C. Wang and G. Xie, "An All-Digital PLL for Video Pixel Clock Regeneration Applications," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 392-396.