Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.772
Based on the switched-capacitor discrete time sampling technique in 0.18um CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The modulator is proved to be robustness, the high performance in stability, anti- mismatch, chip area, and the power consumption is only 2.6mw when the power supply is 2.8V.
sigma-delta modulators; structure of modul- ators; index of circuit module
D. Hua, C. Yueyang and Z. Shun'an, "Design of A Low-Power-Consumption and High-Performance Sigma-Delta Modulator," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 375-379.