Implementation and Quantitative Analysis of a Shared-Memory Based Parallel Server Architecture for Aerospace Information Exchange Applications
Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.509
This paper focuses on the implementation and quantitative analysis of a high-performance parallel processing aerospace information server. An innovative model of software architecture is provided to effectively utilize the computational power of a parallel server platform for efficient, on-demand aerospace information exchange through the Internet. This is a representative application for servers whose features are common to the classical client-server model. The server architecture supports thread, core, and/or processor-level parallel processing for high performance computing. Memory devices (i.e. cache memory, main memory, and secondary memory) are either shared or distributed among the computational units. Such features facilitate our study of identifying and overcoming the architectural bottlenecks of current commercial server configurations.
Aerospace, quantitative analysis, high performance server, parallel processing, bottleneck, runtime, tuple space, hashing, wavelet compression, image transmission
A. Alegre, C. Liu, H. Boussalis, J. Estrada, S. Beltran and A. Milshteyn, "Implementation and Quantitative Analysis of a Shared-Memory Based Parallel Server Architecture for Aerospace Information Exchange Applications," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 359-363.