Computer Science and Information Engineering, World Congress on (2009)
Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.535
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for Plus Width Module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units(logic elements in FPGAs) to calculate the counts of the frequency and the duty cycle, the software only write the period (Hz units) to the period register and the duty cycle (% units) to its register. This presented peripheral for the Nios II system is used successfully in FPGA, and the CPU's runtime can be saved effectively.
PWM, Avalon Bus, Nios II, Verilog HDL
Y. Xu and M. Xiang, "Design a New Type PWM Peripherals in Nios II," 2009 WRI World Congress on Computer Science and Information Engineering, CSIE(CSIE), Los Angeles, CA, 2009, pp. 442-446.