2015 IEEE 18th International Conference on Computational Science and Engineering (CSE) (2015)
Oct. 21, 2015 to Oct. 23, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSE.2015.54
To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.
Field programmable gate arrays, Hardware, Computer architecture, Acceleration, Design tools, Architecture, Performance evaluation
C. B. Ciobanu et al., "EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing," 2015 IEEE 18th International Conference on Computational Science and Engineering (CSE), Porto, Portugal, 2015, pp. 339-342.