2014 IEEE 17th International Conference on Computational Science and Engineering (CSE) (2014)

Chengdu, China

Dec. 19, 2014 to Dec. 21, 2014

ISBN: 978-1-4799-7980-6

pp: 1868-1871

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSE.2014.342

ABSTRACT

Multiplier is the most commonly used circuit in digital devices. Multiplication is one of the basic functions used in digital signal processing. Gate Diffusion Input (GDI) logic reduces the power dissipation and area of digital circuits while maintaining low complexity of logic design. In this paper, GDI technique is used for low-power design of 8-bit multiplier. Reduction in power and area can be achieved using Booth encoding and Wallace tree technique since they generate partial products efficiently and are most suited for multiplication of signed numbers. Multiplier designed in GDI logic requires lesser number of devices as compared to CMOS logic [3]. Hence, GDI multiplier substantially dissipates lesser power as compared to CMOS design.

INDEX TERMS

Logic gates, CMOS integrated circuits, Adders, CMOS technology, Generators, Inverters, Power dissipation

CITATION

B. M. Reddy, H. Sheshagiri, B. Vijayakumar and S. S, "Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic,"

*2014 IEEE 17th International Conference on Computational Science and Engineering (CSE)*, Chengdu, China, 2014, pp. 1868-1871.

doi:10.1109/CSE.2014.342

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