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2012 IEEE 15th International Conference on Computational Science and Engineering (2012)
Paphos, Cyprus Cyprus
Dec. 5, 2012 to Dec. 7, 2012
ISBN: 978-1-4673-5165-2
pp: 407-412
ABSTRACT
As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.
INDEX TERMS
System recovery, System-on-a-chip, Program processors, Bandwidth, Load management, Throughput, Scalability, Load Balance, NoC, Cache Coherence, Deadlock
CITATION

L. Chen, G. Zhang, H. Wang, W. Wang, L. Li and H. Jing, "MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors," 2012 IEEE 15th International Conference on Computational Science and Engineering(CSE), Paphos, Cyprus Cyprus, 2012, pp. 407-412.
doi:10.1109/ICCSE.2012.63
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