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IEEE Symposium on Low-Power and High-Speed Chips. 2013 COOL Chips XVI (2013)
Yokohama
April 17, 2013 to April 19, 2013
ISBN: 978-1-4673-5780-7
TABLE OF CONTENTS

Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor (Abstract)

H. Kobayashi , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
K. Kato , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
T. Ohmaru , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
S. Yoneda , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
T. Nishijima , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
S. Maeda , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
K. Ohshima , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
H. Tamura , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
H. Tomatsu , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
T. Atsumi , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
Y. Shionoiri , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
Y. Machashi , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
J. Koyama , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
S. Yamazaki , Semicond. Energy Lab. Co., Ltd., Atsugi, Japan
pp. 1-3

RXv2 processor core for low-power microcontrollers (Abstract)

S. Otani , Renesas Electron. Corp., Itami, Japan
N. Ishikawa , Renesas Electron. Corp., Itami, Japan
H. Kondo , Renesas Electron. Corp., Itami, Japan
pp. 1-3

Panel discussions the next step in processor evolution (Abstract)

B. Gyselinckx , IMEC, Eindhoven, Netherlands
M. McCool , Intel, Santa Clara, USA
J. Myers , ARM, Cambridge, UK
pp. 1-2

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface (Abstract)

N. Miura , Keio Univ., Yokohama, Japan
Y. Koizumi , Keio Univ., Yokohama, Japan
E. Sasaki , Keio Univ., Yokohama, Japan
Y. Take , Keio Univ., Yokohama, Japan
H. Matsutani , Keio Univ., Yokohama, Japan
T. Kuroda , Keio Univ., Yokohama, Japan
H. Amano , Keio Univ., Yokohama, Japan
R. Sakamoto , Tokyo Univ. of Agric. & Technol., Tokyo, Japan
M. Namiki , Tokyo Univ. of Agric. & Technol., Tokyo, Japan
K. Usami , Shibaura Inst. of Technol., Tokyo, Japan
M. Kondo , Univ. of Electro-Commun., Chofu, Japan
H. Nakamura , Univ. of Tokyo, Tokyo, Japan
pp. 1-3

A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling (Abstract)

Junyoung Park , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Injoon Hong , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Gyeonghoon Kim , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Youchang Kim , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Kyuho Lee , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Seongwook Park , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Kyeongryeol Bong , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Hoi-Jun Yoo , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
pp. 1-3

Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors (Abstract)

K. Ishizaka , NEC Corp., Kawasaki, Japan
T. Miyamoto , NEC Corp., Kawasaki, Japan
S. Akimoto , NEC Corp., Kawasaki, Japan
A. Iketani , NEC Corp., Kawasaki, Japan
T. Hosomi , NEC Corp., Kawasaki, Japan
J. Sakai , NEC Corp., Kawasaki, Japan
pp. 1-3

Automatic parallelization, performance predictability and power control for mobile-applications (Abstract)

D. Hillenbrand , Green Comput. Syst. Res. Organ., Waseda Univ., Tokyo, Japan
A. Hayashi , Green Comput. Syst. Res. Organ., Waseda Univ., Tokyo, Japan
H. Yamamoto , Green Comput. Syst. Res. Organ., Waseda Univ., Tokyo, Japan
K. Kimura , Green Comput. Syst. Res. Organ., Waseda Univ., Tokyo, Japan
H. Kasahara , Green Comput. Syst. Res. Organ., Waseda Univ., Tokyo, Japan
pp. 1-3

HW/SW approaches to accelerate GRAPES in an FU array (Abstract)

Wei Wang , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Jun Yao , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
Youhui Zhang , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Wei Xue , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Y. Nakashima , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
Weimin Zheng , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
pp. 1-3

Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler (Abstract)

Y. Kanehagi , Grad. Sch. of Fundamental Sci. & Eng., Waseda Univ., Tokyo, Japan
D. Umeda , Grad. Sch. of Fundamental Sci. & Eng., Waseda Univ., Tokyo, Japan
A. Hayashi , Grad. Sch. of Fundamental Sci. & Eng., Waseda Univ., Tokyo, Japan
K. Kimura , Grad. Sch. of Fundamental Sci. & Eng., Waseda Univ., Tokyo, Japan
H. Kasahara , Grad. Sch. of Fundamental Sci. & Eng., Waseda Univ., Tokyo, Japan
pp. 1-3

Hardware support for resource partitioning in real-time embedded systems (Abstract)

T. Honmura , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
Y. Kondoh , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
T. Yamada , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
M. Takada , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
T. Nitoh , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
T. Nojiri , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
K. Toyama , Central Res. Lab., Hitachi, Ltd., Kanagawa, Japan
Y. Saitoh , Renesas Electron. Corp., Tokyo, Japan
H. Nishi , Renesas Electron. Corp., Tokyo, Japan
M. Sato , Grad. Sch. of Eng., Tokyo Univ. of Agric. & Technol., Tokyo, Japan
M. Namiki , Grad. Sch. of Eng., Tokyo Univ. of Agric. & Technol., Tokyo, Japan
pp. 1-3

A flexible insertion policy for dynamic cache resizing mechanisms (Abstract)

M. Sato , Cyberscience Center, Tohoku Univ., Sendai, Japan
Y. Tobo , Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
R. Egawa , Cyberscience Center, Tohoku Univ., Sendai, Japan
H. Takizawa , Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
H. Kobayashi , Cyberscience Center, Tohoku Univ., Sendai, Japan
pp. 1-3

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links (Abstract)

Hao Zhang , Keio Univ., Yokohama, Japan
H. Matsutani , Keio Univ., Yokohama, Japan
M. Koibuchi , NII Japan, Japan
H. Amano , Keio Univ., Yokohama, Japan
pp. 1-3

Architecture level TSV count minimization methodology for 3D tree-based FPGA (Abstract)

V. Pangracious , LIP6, Univ. of Pierre & Marie Curie Paris, Paris, France
H. Mehrez , LIP6, Univ. of Pierre & Marie Curie Paris, Paris, France
Z. Marakchi , FlexRas Technol. Paris, Paris, France
pp. 1-3
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